Verilog, can't generate bitstream

Question

First timer in Vivado Verilog here, I just finished my coding for a project and simulation for the project. I keep getting error message when trying to generate bitstream... I think my syntax is correct, just can't figure out what's wrong. This is picture of design that I try to code.

This is project code.

`timescale 1ns/1ps

module project7_demo(
input A,
input B,
input C,
output X
);
wire N1,N2,N3;

assign #1 N1 = A & B;
assign #1 N2 = ~B;
assign #1 N3 = N2 & C;
assign #1 X = N1 | N3;

endmodule

This is simulation code for the project.

`timescale 1ns/1ps

module project7_demo_sim;
reg A_sim;
reg B_sim;
reg C_sim;
wire  X_sim;
wire  N1_sim;
wire  N2_sim;
wire  N3_sim;

project7_demo ASIM (A_sim,B_sim,C_sim,X_sim,N1_sim,N2_sim,N3_sim);
integer k = 0;
initial
begin
A_sim = 0;
B_sim = 0;
C_sim = 0;

for(k=0; k<4; k=k+1)
begin
{A_sim,C_sim} = k;
#5 B_sim=1;
#5 B_sim=0;
#5 ;
end
end

endmodule

It doesn't show that I have syntax error.... But I feel like the errors are from the simulation code? Any help would be appreciated. Thank you.

Did you do what the message tells you to do: check the TCL console output? — Oldfart, Nov 20 '19 at 07:31
um... sorry I don't know what TCL console output is... but this is another error message I get. ERROR: [VRFC 10-2922] 'project7_demo' expects 4 arguments [C:/EE202/project_7/project_7.srcs/sim_1/new/project7_demo_sim.v:12] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. — Javanewbie, Nov 20 '19 at 07:44
Sorry but you have to do some work yourself. Your are making basic mistakes, don't know how to use the tools and do not read the error messages which are very, very clear. We can't hold your hand every step of the way. You if you show some effort, which unfortunately you do not. — Oldfart, Nov 20 '19 at 08:10
There are some tabs (which will be near the bottom of your screen assuming you haven't changed the layout). One is labelled "Tcl Console". This is where Vivado displays its error messages. — Matthew Taylor, Nov 20 '19 at 08:30

score 0 · Answer 1 · answered Nov 20 '19 at 08:46

How to read error message : The error message "ERROR: [VRFC 10-2922] 'project7_demo' expects 4 arguments" says that project7_demo expects 4 arguments and error is in project7_demo_sim.v line 12. Going to that line, we can see that you have declared project7_demo ASIM (A_sim,B_sim,C_sim,X_sim); which is basically 7 arguments.

Correct one is project7_demo ASIM (A_sim,B_sim,C_sim,X_sim);

PS: You seriously need to read some user guides/ text books to understand the concepts. bitfile generation and simulation are different. You are getting this error in simulation which is completely different than bit file generation.

Verilog, can't generate bitstream

1 Answers1