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I was wondering if there is any way to pass a single row of a 2d array of values as the input to a module in Verilog.

Say my array is defined like this:

   reg[15:0] arr[0:9][0:63];
   ...
   ...
   mod1 m(..., arr[5], ....);

mod1 has the definition of:

module mod1 (..., input[15:0] arr[0:63],...);
...
...
endmodule

I use icarus verilog as my compiler. When I compile using the -g2012 flag, it throws the following error:

assert: elaborate.cc:1456: failed assertion rval_net->pin_count() == prts[0]->pin_count()

Can someone help me with this?

toolic
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Akilesh Kannan
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1 Answers1

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iverilog's SystemVerilog support is limited. With the -g2012 flag enabled it can pass multi-dimensional arrays across ports. The version you are using and the version available on EDAplayground, cannot automatically convert multi-dimensional structure into another multi-dimensional structure. This is a tool limitation, not a limitation in the IEEE1800 LRM.

With the version available to me (which is from 2014), I had to create an intermediate translation.

reg[15:0] arr[0:9][0:63];
reg[15:0] arr5[0:63];
...
always @* begin // should be always_comb; 2014 version does not support it
  foreach(arr5[idx])
    arr5[idx] = arr[5][idx];
end
...
mod1 m(..., arr5, ....);
Greg
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