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I am trying to perform subtraction when ALX is 1 and ALY is 0 using instantaneous carry look ahead adder but it does not work properly. It works fine for addition.

  • if ALX is 0 and ALY is also 0 it will load input to output
  • if ALX is 0 and ALY is 1 it will add input to output
  • if ALX is 1 and ALY is 0 it will sub input to output
  • if ALX is 1 and ALY is also 1 it will and input to output

Here is some of my alu module

module alu (CLK, RST, ALE, ALX , ALY, iDATA, oDATA , flags,aDATA);
input wire CLK, ALE, ALX, ALY,RST;
input wire [3:0] iDATA;
output reg [3:0] oDATA;
output reg [3:0] flags;
output reg [2:0] aDATA;

//declare variables

reg [3:0] nextflags;
wire [3:0] ALU;
wire [3:0] SUM;
wire CIN;
wire claCF,claZF,claNF,claVF;

cla4 test(iDATA,oDATA,CIN,SUM,claCF,claZF,claNF,claVF);
assign CIN = ALX;
assign ALU = ALX ? (ALY ? iDATA & oDATA : SUM) : (ALY ? SUM : iDATA ); //loop 
always @ (posedge CLK, posedge RST) begin
if (RST) begin
oDATA <= 0;
flags <= 0;
end

else if(ALE) begin
oDATA <= ALU;
flags <= nextflags;
end

else begin
oDATA <= oDATA;
flags <= flags;
end

always @ (*) begin
aDATA[2:0] = {ALE,ALX,~CIN};
nextflags[3] = ALX ? ( ALY ? flags[3]: claCF ) : (ALY ? claCF : 0 );
nextflags[2] = (ALU==0);
nextflags[1] = ALU[3];
nextflags[0] = ALX ? ( ALY ? flags[0] : claVF ) : (ALY ? claVF : 0 );
end
endmodule

Here is my output

 time:                   0 OUTPUT:0000 ADATA:001 C:0 Z:0 N:0 V:0 
 time:                   1 OUTPUT:0000 ADATA:110 C:0 Z:0 N:0 V:0 
 time:                   2 OUTPUT:0001 ADATA:110 C:1 Z:0 N:0 V:0 
 time:                   4 OUTPUT:0000 ADATA:110 C:1 Z:1 N:0 V:0 
 time:                   6 OUTPUT:0001 ADATA:110 C:1 Z:0 N:0 V:0 
 time:                   8 OUTPUT:0000 ADATA:110 C:1 Z:1 N:0 V:0 
 time:                  10 OUTPUT:0001 ADATA:110 C:1 Z:0 N:0 V:0 
 time:                  12 OUTPUT:0000 ADATA:110 C:1 Z:1 N:0 V:0 
 time:                  14 OUTPUT:0001 ADATA:110 C:1 Z:0 N:0 V:0 
 time:                  16 OUTPUT:0000 ADATA:110 C:1 Z:1 N:0 V:0 
 time:                  18 OUTPUT:0001 ADATA:110 C:1 Z:0 N:0 V:0 
 time:                  20 OUTPUT:0000 ADATA:110 C:1 Z:1 N:0 V:0
Lau Chok Yip
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2 Answers2

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would you provide the complete code? it's hard to find the bug because of the IO naming.

you have a sequential circuit so you must first wait for the rising edge of the clock then check for the changes in control signals(ALY, ALX) then finally propagate the data signals to the combinational circuit (cla4). So, you must implement the fourth line in the always block.

btw, it's better to avoid using multiple conditions on an assign statement unless your 100% sure it's correct.

in the always block you can use a case statement :

   always @ (posedge CLK, posedge RST) begin
if (RST) begin
oDATA <= 0;
flags <= 0;
end

else 
    case({ALX ,ALY}) 
        2'b00 : begin /* */ end
        2'b10 : begin /* */ end
        2'b01 : begin /* */ end
        2'b11 : begin /* */ end



    endcase
   end
M12421K
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    Hi I have edited it. I didn't not use a reg for ALX and ALY though. – Lau Chok Yip Apr 21 '19 at 23:32
  • why not? aren't they updated each clock? ( the circuit reacts to them each clock.) if you think of them as an RTL component in your design you may have two DFFs. – M12421K Apr 22 '19 at 04:20
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I made a stupid mistake and I fixed it by changing the oDATA and iDATA location for the carry look ahead adder function calling 

cla4 test(oDATA,iDATA,CIN,SUM,claCF,claZF,claNF,claVF);

because in my carry look ahead adder module, I declare the first variable as the variable who needs to be added to.

module cla4 (X,Y,M,S,CF,ZF,NF,VF);

assign G = X & (Y ^ {4{CIN}});
assign P = X ^ (Y ^ {4{CIN}});

so the output will be running into a loop because it will basically xor it with carry in to itself. The value just changing back and forth between xor value and its original value.

Lau Chok Yip
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