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Questions tagged [iverilog]

`iverilog` is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing.

iverilog is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing. The currently supported targets are vvp for simulation, and fpga for synthesis. Other target types are added as code generators are implemented.

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How to fix my current MIPS 32 SCP Register File's clock/data errors

I'm building a Single Cycle Processor for a class assignment in Verilog and I can't seem to get the correct output with my test bench. I've got everything wired correctly and it is producing zeros for the first half of my test bench like it should,…
Barnabas Bullion
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Why is iverilog complaining about my testbench module?

I'm writing a verilog module for my CompSci class and this module specifically is the data memory module. Structurally and analytically, I'm looking at it and it should work based off of the other files that I have, but I'm not sure why this one…
Barnabas Bullion
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How to Overcome "warning: Port 8 (Destination) of instruction_reg expects 8 bits, got 1." in verilog?

My task is to implement a Processor with Data Memory using verilog. Instructions are hard coded (32 bit instructions). I have completed inserting a Data Memory. For load and store instructions But when complied i get- "warning: Port 8 (Destination)…
Amila Weerasinghe
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iverilog errors likely stemming from incorrect variable types

I am new to verilog programming and am working on implementing an 8-bit unsigned magnitude comparator using 2 4 bit comparators. I believe my code is implemented correctly, however I am recieving errors which I believe are due to incorrect variable…
mkohler
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Can anyone explain the usage of "$sreadmemh" in SystemVerilog? I don't get clear explanation anywhere

Pls Explain how this code work... module top; //string mem [5]; real mem [5]; initial begin $sreadmemh(mem,2,3,"A","B"); $display("mem = %p",mem); end endmodule
subh
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What should be the output in the following case?

What should be the o/p in the following case? I have run it on different compilers, got different results in each. module top; reg a,b; function int f(string s); $display("%s", s); return 1; endfunction initial…
subh
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Faulty outputs for JK flip flop state diagram implementation

I am trying to implement a simple FSM of JK flip flop in verilog. However I see that the outputs 'q' and 'q_not' are wrong for multiple time instants. I am presenting the code and the output below. Could some one please let me know what's wrong with…
Yaswanth
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How to give the output of one module to be used as an input by another module in verilog?

//code for alu module alu(result,A,B,control); output reg [0:31] result; input [0:31] A; input [0:31]B; input [0:5]control; always @(*) begin case(control) //F0 f1 ena enb inva inc…
Arpit Bal
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Signals not going forward from initial state in Verilog test bench

I am working with a system of two d_flipflops (DFFs) connected to each other (with output,q, of first DFF connected to input,d, of second flipflops. I created sub-modules of DFFs and embedded them into a top module. I then created a test bench.…
Yaswanth
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Error in compilation: Replication operator in Verilog

I am writing verilog code (behavioural) for a 16-bit ALU. I am facing compilation error: module alu_16bit(out,a,b,op); output reg [15:0] out; input [15:0] a,b; input [2:0] op; reg [15:0] e ; reg [15:0] d ; parameter op_add = 3'b000 ; parameter…
Mohit Garg
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iverilog recursive function causes segmentation fault

Here's the problematic code: function automatic [31:0] W; input [6:0] param; W = (param<16) ? 32'b0 : W(param-7); endfunction Basically, iverilog (Icarus Verilog) just gives me a Segmentation fault: 11 vvp svsim error. I tried a bit of…
unixb0y
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Bit shifting in sequential block fails, in combinational not. Why?

I am debugging a piece of Verilog code for days, particularly sending and receiving bytes from an FX2LP (Cypress CY7C68016A) USB controller. Without going into many details, data is sent and transmitted byte-wise in each cycle. For my test, I use a…
divB
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Order of wire statements change behavior

I have the following data transition in my state machine: wire VALID_PKT = (FIFO_DATAIN[7] == 1) & (FIFO_DATAIN[6] == 0)& (FIFO_DATAIN[5] == 1) & (FIFO_DATAIN[1] == 1) & (FIFO_DATAIN[0] == 1); wire SET_RESET = FIFO_DATAIN[3]; reg RESET; always @(*)…
divB
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Test Bench not reaching last test case in verilog

I wrote the following test bench to test my Verilog code: module HalfAdder_Test; wire sum; wire carry; reg a = 0; reg b = 0; initial begin $dumpvars(0, HalfAdder_Test); # 10 a = 0; b = 0; # 30 a = 1; b = 0; # 50 a = 0; b = 1; #…
Tyler Hilbert
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Turn 2 bit module (Multiplier) into more bits

I have the following code for a 2 bit multiplier: module Multiplier (a0, a1, b0, b1, c[3:0]); output [3:0]c; input a0, a1, b0, b1; wire a0b1, a1b0, ha0c, a1b1; and (c[0], a0, b0); and (a0b1, a0, b1); and (a1b0, a1,…
Tyler Hilbert
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