Questions tagged [xilinx]

Xilinx is a major brand of Field Programmable Gate Arrays (FPGA) and CPLDs (Complex Programmable Logic Devices)

Xilinx is known for its fpga devices:

Spartan
Virtex
Kintex
Artix
Zynq Portfolio: System on Chip device along with a FPGA
Versal: 7nm adaptive compute acceleration platform (ACAP)

And the software tools it offers:

Vivado HLS: IP creation using C, C++ and System C
Vivado IP Integrator: create, configure and integrate IPs
System Generator: define, implement and test DSP algorithms
Vitis: embedded software and accelerated applications development
Vitis AI: AI inference stack to run neural networks

With intellectual properties like microblaze soft processor.

Useful links

Website: https://www.xilinx.com
Knowledge base: https://www.xilinx.com/support.html#knowledgebase
Documentation: https://www.xilinx.com/support.html#documentation
Forum: https://forums.xilinx.com
Versal info.

1399 questions

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1 answer

Verilog help. Simple syntax error according to ISE. programing FSM to a basys board

Sorry if this type of question is already up. I've been looking for a couple days now for help on this. I'm getting an error near the parameter line. says ERROR:HDLCompiler:806 - Syntax error near ";". and another error near case(State) Syntax error…

verilog xilinx fsm

asked Apr 03 '13 at 01:52

joinx

-2

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1 answer

How to get pass this synthesizing phase?

When only synthesizing my VHDL program on xilinx 13.2, xilinx synthesized at this portion for a very long time (> a few hours). This is abnormally long since it usually takes 20 mins for a decent machine to synthesize code. Any tips as to how to…

vhdl xilinx

asked Nov 14 '12 at 18:46

Ice

-3

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0 answers

What USB 2.0 IP for FPGA do you recommend?

I am working in a design that includes USB 2.0 development with ULPI interface (USB3343 chip). As I am using Xilinx Spartan 7, I am considering to use the vendor's USB 2.0 IP, but Xilinx is not answering my request for IP cost (it's paid). I would…

ip usb fpga xilinx

asked Aug 18 '23 at 02:49

Gabriel Fpga

-3

votes

1 answer

How to disable Autonegotiation process in petalinux?

I need to disable autonegotiation phase on boot sequence in Petalinux 2019.2. Is there any idea about it? As all you know, an autonegotiation phase is starting automatically by boot sequence and if there is a network dedicates IP for devices this…

networking embedded xilinx u-boot petalinux

asked May 10 '22 at 04:49

muradaltay

-3

votes

1 answer

d[7:0] is an input vector, which shows to be ZZ in the simulation waveform. When does such a situation arise in a Xilinx Vivado simulation?

d[7:0] is an input vector, which shows to be ZZ in the simulation waveform. When does such a situation arise in a Xilinx Vivado simulation ? What mistake I might have made which is resulting in this error ?

verilog xilinx vivado

asked Nov 06 '19 at 07:20

Birjit

-3

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1 answer

Sequential element is unused and will be removed from module in vivado

I am getting a warning that says [Synth 8-3332] Sequential element (\i_data_1_vect_1_reg[31] ) is unused and will be removed from module cg_top in vivado. But the simulation is working fine. I would be great if someone shares why these warnings…

verilog fpga xilinx synthesis vivado

asked Jun 04 '18 at 08:12

kuladeepsai reddy

-3

votes

1 answer

I m trying to synthetize any simple project in ISE for virtex 6. When I generated my synthesis report ,no minimum period was calculated

I am running a project on xilinx 14,1 in virtex 6 . I generated synthesis report. while viewing i couldn't find minimum period.. please help? Speed Grade: -3 Minimum period: No path found Minimum input arrival time before clock: 15.397ns Maximum…

verilog fpga xilinx spartan virtex

asked Apr 10 '18 at 20:16

Vaibhav Gera

-3

votes

2 answers

LOC constraints of Spartan Mimas V2 Development Board for FFT v7.1

ERROR:MapLib:30 - LOC constraint D7 on xn_index<8> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:30 - LOC constraint F7 on xn_index<7> is invalid: No such site…

vhdl fpga xilinx

asked Mar 04 '16 at 20:25

Kunal Bansal

-3

votes

1 answer

how to write code for this?

In Verilog HDL describe a hardware that is able to generate a clock frequency f 0 of approximately 3Hz. Display this clock by connecting it to LED LD7 to verify your approach. I tried a lot but not able to get right output. Device:-Basys2 Spartan3e

verilog fpga xilinx spartan

asked Nov 12 '15 at 19:33

Massnk Dev

-3

votes

1 answer

Custom IP over an AXI bus

I have a Xilinx Zybo board. I followed the instructions here and created a custom multiplier over the AXI bus. The multiplier shown on the website processes one input and generates one output. How can I modify it such that it can process streaming…

fpga xilinx amba

asked Oct 19 '15 at 22:51

zer0c00l

-3

votes

1 answer

Verilog Calculator w/ 16 bit signed inputs

I need to build a calculator that takes 2 signed 16 bit numbers (in1, in2) and preforms functions on them depending on the opCode (a 4 bit input). The outputs should be a signed 16 bit number named 'result' and one bit 'overflow' I really need help…

verilog xilinx hdl circuit

asked Oct 06 '15 at 21:31

Hannah Marie Halverson

-3

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2 answers

Need help VHDL in Xilinx

So, I'm making a college project where I have to make the VHDL simulation of 3 counters using Xilinx. One of the counters goes from 5 down to 0, the other goes from 4 down to 0 and the other goes from 13 to 0, but it counts twice with one clock…

vhdl xilinx

asked Jan 06 '15 at 00:27

pmff96

-3

votes

1 answer

Verilog for error while synthesizing

When I try to synthesize my verilog project i get the following errors: ERROR:Xst:2634 - "shiftman.v" line 15: For loop stop condition should depend on loop variable or be static. ERROR:Xst:2634 - "shiftman.v" line 22: For loop stop condition should…

verilog xilinx

asked Nov 12 '14 at 19:25

yonutix

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1 answer

How to Interface 16 * 2 LCD(HD44780) using Verilog to FPGA/CPLD?

I want to interface a 16 character * 2 line LCD (HD44780) to my FPGA board using Verilog HDL. The program I wrote does not work at all and I don't know why, even though I made a state machine and inserted delays. Note that I used 8 bit mode. Here is…

verilog fpga xilinx system-verilog intel-fpga

asked Feb 06 '14 at 17:48

Shrikant Vaishnav

-4

votes

1 answer

How to resolve syntax errors in this RSA implementation using Verilog?

I am trying to implement RSA on and virtex 5 FPGA using verilog. Xilinx ISE logs aren't very descriptive. I'm using a CORDIC 4.0 IP core and a Random number generator. I've been working on this for the past week and I can't seem to get it…

verilog fpga xilinx

asked Jun 24 '16 at 06:52

Prateek

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