Questions tagged [xilinx]

Xilinx is a major brand of Field Programmable Gate Arrays (FPGA) and CPLDs (Complex Programmable Logic Devices)

Xilinx is known for its fpga devices:

Spartan
Virtex
Kintex
Artix
Zynq Portfolio: System on Chip device along with a FPGA
Versal: 7nm adaptive compute acceleration platform (ACAP)

And the software tools it offers:

Vivado HLS: IP creation using C, C++ and System C
Vivado IP Integrator: create, configure and integrate IPs
System Generator: define, implement and test DSP algorithms
Vitis: embedded software and accelerated applications development
Vitis AI: AI inference stack to run neural networks

With intellectual properties like microblaze soft processor.

Useful links

Website: https://www.xilinx.com
Knowledge base: https://www.xilinx.com/support.html#knowledgebase
Documentation: https://www.xilinx.com/support.html#documentation
Forum: https://forums.xilinx.com
Versal info.

1399 questions

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votes

1 answer

Asynchronous reset warning issue

This design contains one or more registers or latches with an active asynchronous set and asynchronous reset. While this circuit can be built, it creates a sub-optimal implementation in terms of area, power and performance. Initial_LFSR2…

verilog xilinx

asked Jun 15 '19 at 16:31

A.Ashraf

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votes

1 answer

tcl file is unable to get environment variable which is set through code

I have set the environment variable through my code using putenv. I am reading the environment variable through tcl file. It seems , in windows this is showing the following Error : can't read "env(myvar)": no such variable, no such variable …

c++ linux windows tcl xilinx

asked Mar 25 '19 at 10:18

vishu

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votes

1 answer

Creating verilog code from schematic

I need to create a verilog code from this schematic. So far I have: module example1 (X, Y, Z, F); input X, Y, Z; output F; wire w1, w2, w3; nand g0 (X, Y); g1 (X, g0); g2 (Y, g0); g3 (Z, g1, g2); g4 (Z, g2, g3); g5 (g3,…

verilog xilinx

asked Feb 05 '18 at 23:41

Jane

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votes

1 answer

ERROR: unable to find numeric literal operator 'operator""U'?

I am using ARM v7 g++ compiler on Vivado and SDK 2017.4. I had the same code working without any problem, but now it is throwing this error after changing something which is not related with this, apparently. I have undone the changes but it still…

c++ xilinx vivado zynq

asked Jan 29 '18 at 20:20

Cerilet

-2

votes

1 answer

Selecting a package in Xilinx ISE project: FPGA Spartan 3 Device XC3S200

While creating project in Xilinx ISE, we have to select a package in project setting after choosing Family and device. Could any one help me, how I can select/know the package in Xilinx ISE project setting for FPGA Spartan 3 Device XC3S200. Thanks…

fpga xilinx spartan

asked Jan 22 '18 at 19:18

Chand Baba

-2

votes

1 answer

Holiday project goals for undergrads with an FPGA?

It's a student project for vacation research, under-grad, not sure how many of us, there'll probably be 4-6, we're motivated. My original proposal was to get an FPGA (on an Artix-7 or Z-board) to run a CID camera sensor as a dumb peripheral, do some…

computer-vision vhdl fpga xilinx edge-detection

asked Aug 16 '17 at 08:03

Stephen Hannam

-2

votes

1 answer

Synthesis Error IN VIVADO HLS

I wrote C++ Program to sum two numbers. During the Simulation I got correct result but in synthesis.Solution1/.autopilot/db/Adder.pragma.1.cpp:1, error. Please let me know, why I am getting that error message during Synthesis.

c++ c xilinx vivado vivado-hls

asked Mar 16 '17 at 08:58

Saras

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votes

1 answer

Looking for library declaration of IP Module

I want to use the Xilinx hardware module of the ICAP controller in my own design. This module uses the following library: library hwicap_v5_00_a; use hwicap_v5_00_a.all; I was looking in the directories as well as subdirectories…

fpga xilinx

asked Oct 25 '10 at 12:48

Martin

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votes

1 answer

im unable to write output to text file in verilog .Please check what it is wrong

module fir_tb; // Inputs reg clk; reg reset; reg [7:0] inp; reg [15:0]rom[1:8001]; reg [15:0]addr=0; // Outputs wire [7:0] outp; // Instantiate the Unit Under Test (UUT) fir uut ( .clk(clk), …

verilog fwrite xilinx test-bench

asked Feb 15 '16 at 14:41

Suguresh Kumar Arali

-2

votes

1 answer

SuperMicro compatible with ZC706 Xilinx Board

We are looking to buy a SuperMicro machine to install the Xilinx ZC706 board on it for a specific project. We wanted to make sure which machine is and which intel processor family ( Haswell or Broadwell ) is compatible with the board? We had a bad…

compatibility xilinx pci-e

asked Jan 17 '16 at 16:22

saman

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votes

1 answer

Android Source Code (any version) compatible for Xilinx ZC 706

I need android source code compatible for Xilinx ZC706 board. Please give me a link of a repository from where I can download. Any version is okay. Also any suggestion will be highly appreciated. Sazal

android kernel android-source xilinx zynq

asked May 25 '15 at 05:52

Musfiq Sazal

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votes

1 answer

Suggesting Implementation of an Algorithm on FPGA

As a course project, I have to implement an algorithm on FPGA. Currently I'm considering arithmetic algorithms and ideas like implementation of 4 basic operators for floating point numbers come to mind. As I'm new to such topics I'd be thankful if…

vhdl verilog xilinx hdl xilinx-ise

asked Apr 18 '15 at 13:19

Ahmad Siavosh

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votes

1 answer

Verilog code to count Number Repetition

I'm writing verilog code for an algorithm,but I have a problem with one module that receives for example:10 binary numbers (4 bits for each one)from previous module (1 input at every positive edge clk) so there are 10 clock cycles to have the 10…

verilog xilinx

asked Dec 04 '14 at 20:52

Sereena

-2

votes

2 answers

How to compare integer values with binary in for loop for Delay Generation in Verilog Synthesis?

Hello Friends I still not know how to Generate Delay in Verilog For synthesis and call it any line in Verilog for synthesis...for finding this I write a code but it not works please help me if you know how to Generate Delay and call in any line like…

verilog fpga xilinx system-verilog

asked Jan 01 '14 at 04:59

Shrikant Vaishnav

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votes

1 answer

Newline in windows

When I use \r\n in Windows, to print a newline in a file, it works if the file is .v, i.e., it's extension is .v. But if the file extension is changed to .ucf, it starts printing some garbage. I do it through Java code. Any help? .v is a…

windows newline xilinx

asked Nov 12 '13 at 12:54

kamalbanga

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