Questions tagged [xilinx]

Xilinx is a major brand of Field Programmable Gate Arrays (FPGA) and CPLDs (Complex Programmable Logic Devices)

Xilinx is known for its devices:

  • Spartan
  • Virtex
  • Kintex
  • Artix
  • Zynq Portfolio: System on Chip device along with a FPGA
  • Versal: 7nm adaptive compute acceleration platform (ACAP)

And the software tools it offers:

  • Vivado HLS: IP creation using C, C++ and System C
  • Vivado IP Integrator: create, configure and integrate IPs
  • System Generator: define, implement and test DSP algorithms
  • Vitis: software and accelerated applications development
  • Vitis AI: AI inference stack to run neural networks

With intellectual properties like microblaze soft processor.

Useful links

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Filo I/O operations from SD card in Xilinx Zynq ZCU102

I'm using a Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. I want to run a C++ program in the Xilink SDK tool(running on a Windows machine) that can do Filo I/O operations on a binary file stored in the SD card in the Zync board. I have the…
Naveen
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How to syntax check VHDL in Vivado without complete synthesis

What's the simplest way to syntax-check my VHDL in Vivado without running through a full synthesis? Sometimes I code many inter-related modules at once, and would like to quickly find naming errors, missing semi-colons, port omissions, etc. The…
edj
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Linux 4.5 GPIO Interrupt Through Devicetree on Xilinx Zynq Platform

I am using a custom development board with a Zynq XC72010 used to run a Linux 4.5 kernel. I am developing a device driver for a chip we are testing in house and I am having a lot of issues trying to bind a GPIO line to a software IRQ. So far I have…
James Schulman
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Does aborting a partial FPGA reconfiguration possibly result in an undefined state?

I'm working on a reconfiguration controller for a reconfigurable CPU. One of the features I tried to implement is to handle CRC errors properly, and also to allow for aborts during reconfiguration. I am using a Virtex7 board and as described in…
rtur
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SP605 Spartan 6 DDR3 addressing

the following post is quite long, but since I have had trouble making the SP605 board properly interact with the DDR3 for over a month now, hopefully this will be useful to others in the same situation as I find myself in. I am pretty certain it's a…
buped82
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Why does an If statement cause a latch in verilog?

I am trying to code a controller/data-path implementation in Verilog, and I am confused on what will cause an unwanted latch. Essentially, I have a state machine updating on the negedge clock. This state machine sends 5 control signals (loadSquare,…
Anthony
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Does C++ runtime always require malloc()?

I have a C++ application running bare-metal that I want to make as small as possible. I am not using dynamic memory allocation anywhere. I am using no STL functions. I've also overridden all the varieties of "delete" and "new" with empty…
Barry Gackle
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how to implement FPGA coprocessing with C/C++ on zynq 7020?

I'm studying vivadoHLS, and the tutorial u871 has introduced how to use HLS, and optimize my C/C++ code. But I want to know how to load them into my board zynq 7020, let it run on board. What I want to implement is : The host (CPU on board) calls…
happybunnie_wy
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Trying to automate the fpga build process in Xilinx using python scripts

I want to automate the entire process of creating ngs,bit and mcs files in xilinx and have these files be automatically be associated with certain folders in the svn repository. What I need to know is that is there a log file that gets created in…
serendipity
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Xilinx Simulation Error Fuse:500

I'm trying to simulate my VHDL code using Xilinx ISim. When I try to generate the testbench for the simulation, the simulator throws up the following error: FATAL_ERROR:Simulator:Fuse.cpp:500:1.133 - Failed to compile generated C file isim/ I tried…
JanFo
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Reduce delay by understanding Xilinx Synthesis report

I am programming the 8051 instruction set in VHDL in Xilinx. After writing the logic and generating the synthesis report, I saw that the Delay is 13.330ns (frequency of 75.020 MHz) with Levels of Logic = 10. This value is pretty less (the frequency)…
Saurabh
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Is there a way to synchronize custom interrupt signals with AXI master transactions in Vitis HLS?

I have been unable to find an answer, possibly due to me being unable to put specific enough nomenclature on the involved processes. I use Vitis HLS to synthesize designs where one call of the main function is one clock cycle long, being pipelined…
PhilMasteG
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How to use an OLED display for an Avnet Virtex4?

I have an Avnet ADS-XLX-V4FX-EVL12-G (Virtex4 Evaluation Board) with OLED display. I used Xilinx EDK 10.1 with Xilinx Platform Studio 10.1 and succeded to upload some basic app to the board (serial communication). Now I would like to use the OLED…
Ionel Bratianu
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Book suggestions for Low-level ethernet/networking (e.g. MII)

I had a colleague who is using Xilinx's LocalLink TEMAC While I find the DS interesting, I would like to learn more about the basics of it. Does anyone have any recommendations for a good low-level intro to networking/ethernet book? I don't need to…
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Warning: VC++ 2008 runtime libraries are not installed. Xilinx

I installed the ISE from Xilinx to my windows PC and it ended up very bad. It isn't working, since when I try to run it, the next message appears Warning: VC++ 2008 runtime libraries are not installed. Please install the runtime libraries by running…
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