how to write code for this?

Question

In Verilog HDL describe a hardware that is able to generate a clock frequency f 0 of approximately 3Hz. Display this clock by connecting it to LED LD7 to verify your approach. I tried a lot but not able to get right output.

Device:-Basys2 Spartan3e

what did you try? Post it here. Well be able to help – letsc Nov 12 '15 at 20:44 — letsc, Nov 12 '15 at 20:44
Also you must have an input clock of some frequency? – Morgan Nov 12 '15 at 22:09 — Morgan, Nov 12 '15 at 22:09

score 1 · Answer 1 · answered Nov 13 '15 at 06:04

I will give the steps(not the code) to create a clock divider which is what you need here.

Say you clock has frequency f. Create a counter which counts from 1 to f/2.
Say your new divided clock name is clk_new. Initialize this clk_new to zero.
Whenever the counter value is in its maximum (which is f/2), toggle clk_new. you can do this by clk_new = ~clk_new; and also reset the counter to zero and let it begin the counting again.

Write the code and if it doesnt work, post here. We can help.

how to write code for this?

1 Answers1