Questions tagged [xilinx]

Xilinx is a major brand of Field Programmable Gate Arrays (FPGA) and CPLDs (Complex Programmable Logic Devices)

Xilinx is known for its fpga devices:

Spartan
Virtex
Kintex
Artix
Zynq Portfolio: System on Chip device along with a FPGA
Versal: 7nm adaptive compute acceleration platform (ACAP)

And the software tools it offers:

Vivado HLS: IP creation using C, C++ and System C
Vivado IP Integrator: create, configure and integrate IPs
System Generator: define, implement and test DSP algorithms
Vitis: embedded software and accelerated applications development
Vitis AI: AI inference stack to run neural networks

With intellectual properties like microblaze soft processor.

Useful links

Website: https://www.xilinx.com
Knowledge base: https://www.xilinx.com/support.html#knowledgebase
Documentation: https://www.xilinx.com/support.html#documentation
Forum: https://forums.xilinx.com
Versal info.

1399 questions

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2 answers

Ideas for a flexible/generic decoder in VHDL

I want to create an address Decoder that is flexible enough for me to use when changing the number of bits of the selector and of the decoded output signals. So, instead of having a static (fixed input/output size) Decoder that looks something like…

vhdl fpga xilinx

asked Jan 24 '11 at 22:29

Erick Tejada

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1 answer

What is the simplest way to transmit a signal over MGT of Xilinx FPGA?

I want to send signals (doesn't matter what type of signal, just random binary) over MGT lanes of a Xilinx FPGA. This is for testing the MGT traces on the PCB. What is the simplest way I can achieve this? For a regular IO I would simply use an…

fpga xilinx

asked Feb 23 '16 at 22:44

Arash Fotouhi

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1 answer

Where does the Xilinx TCL shell emit the results?

I'm trying to develop a Python based wrapper around the Xilinx ISE TCL shell xtclsh.exe. If it works, I'll add support for other shells like PlanAhead or Vivado ... So what's the big picture? I have a list of VHDL source files, which form an IP…

python shell subprocess xilinx xilinx-ise

asked Dec 16 '15 at 22:34

Paebbels

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3 answers

How to send data to AXI-Stream in Zynq from software tool?

I'm looking for a way to send some data from my software app written in C to AXI-Stream interface of Zynq. Something like open(/dev/axistream); send_data(data); I'm running Linux on the Arm part and now I want to connect it to the programmable…

linux arm fpga xilinx zynq

asked Jun 02 '15 at 13:25

Viktor Puš

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8 answers

Error in VHDL (Xilinx): failed to link the design

why I get error in VHDL for this? Also, sometimes: cannot do process as a process failed previously? Many thanks.

vhdl xilinx

asked Apr 12 '14 at 16:45

user3527245

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1 answer

Verilog: value(s) does not match array range, simulation mismatch

The following code synthesizes and simulates correctly as far as I can tell, but XST is still giving the following warning: value(s) does not match array range, simulation mismatch. Is there something I'm missing? Tool used: Xilinx ISE Project…

verilog xilinx hdl

asked Mar 06 '14 at 05:33

verigolfer

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2 answers

Weird XNOR behaviour in VHDL

The code that is causing problems looks like a normal xnor operation as you can see below: S(1) <= L(16) xnor L(26); This line causes the following error: ncvhdl_p: *E,EXPSMI (HDL/aes_sbox_enc_depth16.vhd,169|14): expecting a semicolon (';')…

vhdl fpga xilinx

asked Feb 14 '12 at 13:05

Patrick

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1 answer

what is the difference between slice registers and slice LUTs in Xilinx FPGA?

What is the difference between "slice registers" and "slice LUTs" in Xilinx FPGA? Why is the number of slice registers equal to the number of slice LUTs in Vertix 5 for example, but the number of slice registers is double the number of slice LUTs in…

fpga xilinx

asked Feb 09 '18 at 23:47

lolo

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1 answer

freeRTOS scheduling configurations for tasks

I have my freeRTOS currently working on my Microzed board. I am using the Xilinx SDK as the software platform and until now I have been able to create tasks and assign priority. I was just curious to know if it would be possible to assign a fixed…

scheduling xilinx freertos

asked Feb 19 '17 at 17:32

Tarik

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1 answer

Relationship between number of logic cells on an FPGA and performance

Hey so I have a question about FPGA's. If you look at the current lineup of xilinx products, specifically the 7 series, there is a massive price differential between each of the models. What I don't understand is if I could buy an Artix-7 with ~200k…

cryptography logic cell fpga xilinx

asked Mar 12 '14 at 20:42

c0mrade_ethan

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2 answers

Synchronous reset design in fpga as the limiting factor for timing constraints

I've got an fpga design that utilizes synchronous resets (I prefer synchronous resets to asynchronous for reasons discussed elsewhere). I have four different clock domains in the design and I utilize a single button to generate my reset signal,…

verilog fpga xilinx

asked May 31 '13 at 19:23

Doov

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3 answers

Using XILINX XPS with Microblaze - quickest way to program the fpga

I'm designing a micro controller based around the microblaze microprocessor on a xilinx fpga. Most of the hardware setup is done. All I'm updating at this point is the c code to be run on the microblaze. Is there a way in XPS to not have to rebuild…

fpga xilinx virtex

asked Sep 04 '09 at 18:50

giroy

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0 answers

Why are the headers not found in the Xilinx SDK?

I am following the course "Introduction to Deep Learning with Xilinx SoCs Technical Training Course" for the Ultra96v2 board and reached Lab No. 5. I am able to follow along until I am supposed to build the project in the SDK. It fails and tells me…

c++ linux eclipse-cdt xilinx zynq-ultrascale+

asked Jan 28 '22 at 15:06

Vandrey

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1 answer

Vivado, Zynq, BRAM Controller, Narrow AXI burst option

Consider a simple system with PS (Processor system) with enabled AXI3 Master, connected to AXI4 Interconnect connected to BRAM Controller that has access to BRAM memory. What is the meaning of AXI Narrow Bursts? How do i define or consider what is…

xilinx vivado zynq axi4

asked Dec 26 '18 at 12:06

CJC

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2 answers

Explicitly define how LUTs and slices are used in Xilinx XST tool?

I'm trying to implement some very specific behavior of LUTs and slices, written in VHDL for Xilinx Virtex 5 FPGA synthesized using XST tool(s). I don't know if I can achieve my behavior by having the tools infer what I mean, so how do I explicitly…

vhdl fpga xilinx

asked Mar 02 '11 at 03:05

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