Verilog for error while synthesizing

Question

When I try to synthesize my verilog project i get the following errors: ERROR:Xst:2634 - "shiftman.v" line 15: For loop stop condition should depend on loop variable or be static. ERROR:Xst:2634 - "shiftman.v" line 22: For loop stop condition should depend on loop variable or be static.

I think I understand what causes the error, but I can't find a way to fix it.

module shiftman(in,sh,out);

input[47:0] in;
input[8:0] sh;
output[47:0] out;
reg[47:0] out;
reg[7:0] r;
reg i;
always@(in or sh)
begin
r=sh[7:0];
out=in;
if(sh[8]==0)
        for(i=0; i<r; i=i+1)
        begin
        out[23:0]={1'b0,out[23:1]};
        end
else
        for(i=0; i<r; i=i+1)
        begin
        out[47:24]={1'b0,out[47:25]};
        end

end

endmodule

Answer 1

The reason your synthesis is failing is because you cannot uses variable-iteration loops in synthesizable code. When synthesizing, the tool will attempt to unroll the loop, but it cannot do this if the termination condition for the loop is not static or determinable at synthesis. Your condition i <= r is such a condition as we cannot unroll the loop without knowing r, which is an input to the module and thus, not static.

In order to fix this, youll need to rewrite your code in a way that the synthesis tool can process. By the looks of it, you are simply logically shifting either the top or bottom of in by sh[7:0] depending on sh[8]. In order to do this, you don't need looping at all, but can use the >> (logical right shift operator). So, your always block would look more like this:

always @(*) begin
  out = in;

  if (sh[8])
    out[47:24] = in[47:24] >> sh[7:0];
  else
    out[23:0] = in[23:0] >> sh[7:0];
end