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When only synthesizing my VHDL program on xilinx 13.2, xilinx synthesized at this portion for a very long time (> a few hours). This is abnormally long since it usually takes 20 mins for a decent machine to synthesize code.

Any tips as to how to get pass this "Analyzing FSM for best encoding." phase ?

Started : "Synthesize - XST". Running xst... Command Line: xst -intstyle ise -ifn "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/i8051_top.xst" -ofn "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/i8051_top.syr" Reading design: i8051_top.prj

========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/constants.vhd" in Library work. Compiling vhdl file "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/ext_interrupt.vhd" in Library work. Architecture behavioral of Entity ext_interrupt is up to date. Compiling vhdl file "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/csadde2.vhd" in Library work. Architecture csadde2beh of Entity csadde2 is up to date. Compiling vhdl file "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/csadder.vhd" in Library work. Architecture csadderbeh of Entity csadder is up to date. Compiling vhdl file "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/sequencer2.vhd" in Library work. Architecture seq_arch of Entity sequencer2 is up to date. Compiling vhdl file "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/fastalu.vhd" in Library work. Architecture fastalu_arch of Entity fastalu is up to date. Compiling vhdl file "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/int_rom.vhd" in Library work. Architecture behavioral of Entity int_rom is up to date. Compiling vhdl file "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/int_ram.vhd" in Library work. Architecture syn of Entity internal_ram is up to date. Compiling vhdl file "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/divider.vhd" in Library work. Architecture rtl of Entity divider is up to date. Compiling vhdl file "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/int_handler.vhd" in Library work. Architecture behavioral of Entity int_handler is up to date. Compiling vhdl file "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/8051_top_fpga.vhd" in Library work. Architecture behavioral of Entity i8051_top is up to date.

========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ).

Analyzing hierarchy for entity in library (architecture ).

Analyzing hierarchy for entity in library (architecture ).

Analyzing hierarchy for entity in library (architecture ).

Analyzing hierarchy for entity in library (architecture ).

Analyzing hierarchy for entity in library (architecture ) with generics. DWIDTH = 16

Analyzing hierarchy for entity in library (architecture ).

Analyzing hierarchy for entity in library (architecture ).

Analyzing hierarchy for entity in library (architecture ).

Analyzing hierarchy for entity in library (architecture ).

Analyzing hierarchy for entity in library (architecture ).

Analyzing hierarchy for entity in library (architecture ).

Analyzing hierarchy for entity in library (architecture ).

========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated.

Analyzing Entity in library (Architecture ). INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register in unit has a constant value of 1111111111111111 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register in unit has a constant value of 1111111111111111 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. Entity analyzed. Unit generated.

Analyzing Entity in library (Architecture ). INFO:Xst:1561 - "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/fastalu.vhd" line 261: Mux is complete : default of case is discarded WARNING:Xst:819 - "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/fastalu.vhd" line 245: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: , , , , Entity analyzed. Unit generated.

Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated.

Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated.

Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated.

Analyzing Entity in library (Architecture ). WARNING:Xst:819 - "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/regfile.vhd" line 89: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: , , , , , , , , , , , , , , , , ,

Analyzing Entity in library (Architecture ). INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. Entity analyzed. Unit generated.

Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated.

=========================================================================

* HDL Synthesis *

Performing bidirectional port resolution...

Synthesizing Unit . Related source file is "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/sequencer2.vhd". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. INFO:Xst:1799 - State e19 is never reached in FSM . INFO:Xst:1799 - State e20 is never reached in FSM . INFO:Xst:1799 - State e21 is never reached in FSM . INFO:Xst:1799 - State e22 is never reached in FSM . INFO:Xst:1799 - State e23 is never reached in FSM . INFO:Xst:1799 - State e24 is never reached in FSM . Found finite state machine for signal . ----------------------------------------------------------------------- | States | 14 | | Transitions | 37 | | Inputs | 23 | | Outputs | 9 | | Clock | clk (rising_edge) | | Reset | rst (positive) | | Reset type | asynchronous | | Reset State | e1 | | Power Up State | e1 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine for signal . ----------------------------------------------------------------------- | States | 6 | | Transitions | 1068 | | Inputs | 177 | | Outputs | 6 | | Clock | clk (rising_edge) | | Reset | rst (positive) | | Reset type | asynchronous | | Reset State | e7 | | Power Up State | e7 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine for signal . ----------------------------------------------------------------------- | States | 6 | | Transitions | 33886 | | Inputs | 361 | | Outputs | 6 | | Clock | clk (rising_edge) | | Reset | rst (positive) | | Reset type | asynchronous | | Reset State | e13 | | Power Up State | e13 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 8-bit register for signal . Found 1-bit register for signal . Found 4-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 1-bit register for signal . Found 16-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 1-bit register for signal . Found 4-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 16-bit register for signal . Found 8-bit comparator not equal for signal created at line 1190. Summary: inferred 3 Finite State Machine(s). inferred 184 D-type flip-flop(s). inferred 1 Comparator(s). Unit synthesized.

Synthesizing Unit . Related source file is "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/multiplier.vhd". Found 32-bit register for signal . Found 16x16-bit multiplier for signal . Summary: inferred 32 D-type flip-flop(s). inferred 1 Multiplier(s). Unit synthesized.

Synthesizing Unit . Related source file is "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/int_rom.vhd". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 4096x8-bit ROM for signal created at line 175. Summary: inferred 1 ROM(s). Unit synthesized.

Synthesizing Unit . Related source file is "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/int_ram.vhd". WARNING:Xst:736 - Found 1-bit latch for signal created at line 38. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:736 - Found 8-bit latch for signal created at line 37. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:736 - Found 1-bit latch for signal created at line 38. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. WARNING:Xst:736 - Found 1-bit latch for signal created at line 37. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. Found 1-bit tristate buffer for signal . Found 8-bit tristate buffer for signal . Found 8-bit 128-to-1 multiplexer for signal created at line 42. Found 8-bit 128-to-1 multiplexer for signal created at line 49. Found 640-bit register for signal >. Found 256-bit register for signal >. INFO:Xst:738 - HDL ADVISOR - 1024 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.

Synthesizing Unit . Related source file is "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/csadder.vhd". WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 1-bit xor3 for signal >. Found 2-bit xor2 for signal . Found 1-bit xor2 for signal created at line 60. Found 3-bit xor2 for signal . Found 1-bit xor2 for signal created at line 82. Found 4-bit xor2 for signal . Found 1-bit xor2 for signal created at line 110. Found 1-bit xor2 for signal created at line 118. Found 1-bit xor2 for signal created at line 124. Found 6-bit xor2 for signal . Found 1-bit xor2 for signal created at line 144. Found 1-bit xor2 for signal created at line 150. Found 1-bit xor2 for signal created at line 156. Found 1-bit xor2 for signal >. Found 2-bit xor2 for signal >. Found 1-bit xor2 for signal created at line 89. Found 3-bit xor2 for signal >. Found 5-bit xor2 for signal >. Found 1-bit xor2 for signal created at line 163. Found 1-bit xor2 for signal created at line 170. Summary: inferred 1 Xor(s). Unit synthesized.

Synthesizing Unit . Related source file is "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/csadde2.vhd". WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 1-bit xor2 for signal >. Found 1-bit xor2 for signal >. Found 2-bit xor2 for signal >. Found 3-bit xor2 for signal >. Found 5-bit xor2 for signal >. Unit synthesized.

Synthesizing Unit . Related source file is "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/ext_interrupt.vhd". WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. Found 8-bit register for signal . Found 4-bit register for signal >. Found 2-bit register for signal >. Found 2-bit register for signal >. Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 10 D-type flip-flop(s). Unit synthesized.

Synthesizing Unit . Related source file is "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/fastalu.vhd". Found 1-bit 4-to-1 multiplexer for signal . Found 1-bit 4-to-1 multiplexer for signal . Found 1-bit 4-to-1 multiplexer for signal . Found 1-bit xor2 for signal created at line 261. Found 1-bit xor2 for signal created at line 258. Found 1-bit xor2 for signal created at line 255. Found 1-bit xor2 for signal created at line 252. Found 8-bit xor2 for signal created at line 210. Found 8-bit xor2 for signal created at line 207. Summary: inferred 3 Multiplexer(s). Unit synthesized.

Synthesizing Unit . Related source file is "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/fastal2.vhd". WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. Unit synthesized.

ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. Found 8-bit register for signal . Found 1-bit tristate buffer for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit tristate buffer for signal . Found 4-bit register for signal >. Found 2-bit register for signal >. Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 2-bit register for signal >. Found 8-bit register for signal . Found 8-bit register for signal . Found 1-bit xor8 for signal created at line 169. Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Summary: inferred 168 D-type flip-flop(s). inferred 1 Xor(s). inferred 9 Tristate(s). Unit synthesized.

Synthesizing Unit . Related source file is "C:/Users/Farmer/Desktop/CG3207 BACKUP/12 Nov 2012/ISA NOMX/8051_top_fpga.vhd". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Unit synthesized.

========================================================================= HDL Synthesis Report

Macro Statistics

ROMs : 1 4096x8-bit ROM : 1

Multipliers : 1 16x16-bit multiplier : 1

Adders/Subtractors : 1 16-bit subtractor : 1

Counters : 1 4-bit down counter : 1

Registers : 453 1-bit register : 306 16-bit register

: 6 3-bit register : 1 32-bit register : 1 4-bit register
: 2 8-bit register : 137

Latches : 8 1-bit latch : 6 8-bit latch

: 2

Comparators : 5 16-bit comparator greatequal : 1 16-bit comparator

not equal : 2 4-bit comparator greater
: 1 8-bit comparator not equal : 1

Multiplexers : 5 1-bit 4-to-1 multiplexer : 3 8-bit 128-to-1

multiplexer : 2

Tristates : 4 1-bit tristate buffer : 2 8-bit tristate

buffer : 2

Xors : 57 1-bit xor2 : 53 1-bit xor3

: 1 1-bit xor8 : 1 8-bit xor2 : 2

=========================================================================

=========================================================================

* Advanced HDL Synthesis *

Analyzing FSM for best encoding.

Ice
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    Can you post the VHDL code in question? Did you find the smallest amount of code that replicates the issue? –  Nov 14 '12 at 19:41
  • Please shorten up your question to just the essential information. The example you posted as an answer should be part of the question. – Bill the Lizard Nov 15 '12 at 13:19

1 Answers1

2

Several points... Pay attention to what the synth tool is telling you : both in messages and otherwise.

0) If you haven't got it working in simulation, STOP HERE and do that now.

1) In your previous question How to deduce from synthesis report it was already clear that your big case statement was giving trouble and I suggested an approach to start simplifying it.

2) If synthesis is taking this long for a CPU that originally took only 20000(?) transistors, you need to do something different.

3) There are warnings about latches and incomplete case coverage in the HUGE and mostly unnecessary list you gave. Find and fix these : they certainly won't help synth converge on a good solution!

4) Look at what each output or group of related outputs do for each opcode or group of opcodes; and you will find huge simplifications. Taking n individual little state machines and mashing them into one huge SM not only gives you an n**2 problem but makes it almost impossible to untangle. For example, a latch problem can be isolated to a much smaller block of code and fixed there; tracing it in this big SM will be ... difficult.

The "one process" model is good style in many circumstances; but it can be taken too far.

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