d[7:0] is an input vector, which shows to be ZZ in the simulation waveform. When does such a situation arise in a Xilinx Vivado simulation?

Question

d[7:0] is an input vector, which shows to be ZZ in the simulation waveform. When does such a situation arise in a Xilinx Vivado simulation ? What mistake I might have made which is resulting in this error ?

score 2 · Answer 1 · answered Nov 06 '19 at 07:53

2

You have never assigned any value to the signal. Check your connections. Also check all your signal names. (Capitalization typos etc.)

answered Nov 06 '19 at 07:53

Oldfart

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d[7:0] is an input vector, which shows to be ZZ in the simulation waveform. When does such a situation arise in a Xilinx Vivado simulation?

1 Answers1