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Sorry if this type of question is already up.
I've been looking for a couple days now for help on this.

I'm getting an error near the parameter line. says ERROR:HDLCompiler:806 - Syntax error near ";". and another error near case(State) Syntax error near "(". but i have a feeling its not an error with the syntax. 

`timescale 1ns / 1ps

module movSeven(Clk, Rst, A, an0, an1, an2, an3 );

input A;

output reg  an0, an1, an2, an3;

input Clk, Rst;

parameter W = 1, X = 2, Y = 3, Z = 4 ;

reg [1:0] State, StateNext;

always @(State, A) begin

    case(State) 
      W:begin
        an0 <= 0;
        if (A == 0)
          StateNext <= W;
        else
          StateNext <= X;
        end

     X:begin
      an1 <= 0;
      if (A == 0)
        StateNext <= X;
      else
        StateNext <= Y;
      end

    Y:begin 
      an2 <= 0;
      if (A == 0)
        StateNext <= Y;
      else
        StateNext <= X;
    end

     Z:begin
      an3 <= 0;
      if (A == 0)
        StateNext <= Z;
      else
        StateNext <= W;
    end
endcase
end

always @(posedge Clk)
begin 
    if (Rst == 1)
      State <= X;
    else
      State <= StateNext;   
    end
endmodule
Tim
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joinx
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  • `always @(posedge Clk or posedge Rst)` – Pulimon Apr 03 '13 at 02:49
  • wow really quick responses. thanks guys!!! i'm getting an error near the parameter line. says ERROR:HDLCompiler:806 - Syntax error near ";". and another error near case(State) Syntax error near "(". but i have a feeling its not an error with the syntax. – joinx Apr 03 '13 at 02:57
  • @Pulimon - It's not required that asynchronous resets be used, the synchronous reset there should be fine. – Tim Apr 03 '13 at 04:03
  • thanks for the edits but for some reason it's still not compiling. And giving me the same error codes. I'm new to this but could it be something to do with something that looks like this: 3'b001, near the variables? Possibly missing them completely? :S thanks again!! – joinx Apr 03 '13 at 04:25
  • Please don't 'summarize' the errors you get, as we're losing a lot of information. If you're stuck on an error, then just copy and paste the entire exact output of your tool. – Tim Apr 03 '13 at 05:10
  • @Tim: ya thats true. My bad. – Pulimon Apr 03 '13 at 05:25

1 Answers1

1

State and StateNext are 2 bits wide. So they cannot have a value = 4 (parameter Z) Also try giving individual lines for each parameter and define them in bit format.

parameter W = 2'b00;
parameter X = 2'b01;
parameter Y = 2'b10;
parameter Z = 2'b11;
Pulimon
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    Good advice, but I don't think this is the source of the original errors. Verilog will silently convert 4 to 2'b00 and press on. –  Apr 03 '13 at 10:39
  • I'm pretty sure comma separated parameters are legal (see pg. 69 here: http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf) – Tim Apr 03 '13 at 16:49