Need help VHDL in Xilinx

Question

So, I'm making a college project where I have to make the VHDL simulation of 3 counters using Xilinx. One of the counters goes from 5 down to 0, the other goes from 4 down to 0 and the other goes from 13 to 0, but it counts twice with one clock signal. The code I developed was something like these (it was based on a schematic so the entity and architecture is supposed to remain untouched I think):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY projetesquema2_projetesquema2_sch_tb IS
END projetesquema2_projetesquema2_sch_tb;
ARCHITECTURE behavioral OF projetesquema2_projetesquema2_sch_tb IS 

COMPONENT projetesquema2
PORT( CLOCK :   IN  STD_LOGIC; 
      ACL   :   IN  STD_LOGIC; 
      CAT   :   OUT STD_LOGIC; 
      CRT   :   OUT STD_LOGIC; 
      CLT   :   OUT STD_LOGIC; 
      ACA   :   IN  STD_LOGIC);
END COMPONENT;

SIGNAL CLOCK    :   STD_LOGIC;
SIGNAL ACL  :   STD_LOGIC;
SIGNAL CAT  :   STD_LOGIC;
SIGNAL CRT  :   STD_LOGIC;
SIGNAL CLT  :   STD_LOGIC;
SIGNAL ACA  :   STD_LOGIC;

BEGIN

UUT: projetesquema2 PORT MAP(
    CLOCK => CLOCK, 
    ACL => ACL, 
    CAT => CAT, 
    CRT => CRT, 
    CLT => CLT, 
    ACA => ACA
);

*** Test Bench - User Defined Section ***

tb : PROCESS
BEGIN
 process (CLOCK)
begin
    if (CLOCK'event and CLOCK='1') then
      if (ACA='0') then
        CAT <= "0000";
      else
        CAT <= CAT + 1;
      end if;
    end if;
 end process;

  process (CAT)
 begin
    if (CAT'event and CAT='1') then
        CRT <= CRT + 1;
      end if;
    end if;
 end process;

  process (CLOCK)
 begin
    if (CLOCK'event and CLOCK='1') then
      if (ACL='0') then
        CLT <= "0000";
      else
        CLT <= CLT + 1;
      end if;
    end if;
 end process;

 end Behavioral;
  WAIT; -- will wait forever
 END PROCESS;
*** End Test Bench - User Defined Section ***

 END;

This gives me some errors that I don't know how to fix, hope somebody can actually help me. Errors are:

ERROR:Line 54: Syntax error near "process".

ERROR:Line 55: Syntax error near "begin".

ERROR:Line 58: Type std_logic does not match with a string literal

ERROR:Line 60: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"

ERROR:Line 68: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"

ERROR:Line 70: Syntax error near "if".

ERROR:Line 77: Type std_logic does not match with a string literal

ERROR:Line 79: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"

ERROR:Line 22: Unit ignored due to previous errors.

ERROR:Line 85: Syntax error near "WAIT".

Answer 1

Assuming the asterisk delimited comments aren't part of the VHDL design specification:

You have an extraneous PROCESS and BEGIN:

tb : PROCESS
BEGIN
 process (CLOCK)
begin

There's an extra end if:

  process (CAT)
 begin
    if (CAT'event and CAT='1') then
        CRT <= CRT + 1;
      end if;
    end if;
 end process;

There are more extraneous statements:

 end Behavioral;
  WAIT; -- will wait forever
 END PROCESS;
-- *** End Test Bench - User Defined Section ***

 END;

This should simply be:

end Behavioral; 

or

end architecture Behavioral;

And now we find semantic errors:

'CAT' is defined as a scalar std_logic:

    SIGNAL CAT  :   STD_LOGIC;
    SIGNAL CRT  :   STD_LOGIC;
    SIGNAL CLT  :   STD_LOGIC;
    SIGNAL ACA  :   STD_LOGIC;

and used in the component declaration for projetesquema2.

You can't promote it to a std_logic_vector value:

        CAT <= "0000";
      else
        CAT <= CAT + 1;

or add an integer to it like it was declared as an unsigned (the use clause references package numeric_std, and BTW the unisim stuff can be dumped).

The same argument hold true for CRT and CLA. projetesquema appears to translate into English as project plan, there is insufficient information to advise an answerer how to fix these issues.

Perhaps if you made the entity and architecture for projetesquema2 available or told us what it does and what the port names mean?

It seems you've either been thrown in the deep end, missed part of your reading list or haven't been paying attention in class from the errors we see so far.

Stackoverflow may not where you should be going as a first resource for learning VHDL, and the Xilinx tools are somewhat unfriendly for error messages.

I know this it's in English but try this reference for an overview of VHDL.

Answer 2

Right around here you start defining a process inside a process, which isn't legal. Nor does it make much sense.

tb : PROCESS
BEGIN
 process (CLOCK)
begin
    if (CLOCK'event and CLOCK='1') then