Highest Voted 'virtex' Questions

6

votes

3 answers

Using XILINX XPS with Microblaze - quickest way to program the fpga

I'm designing a micro controller based around the microblaze microprocessor on a xilinx fpga. Most of the hardware setup is done. All I'm updating at this point is the c code to be run on the microblaze. Is there a way in XPS to not have to rebuild…

fpga xilinx virtex

asked Sep 04 '09 at 18:50

giroy

2,203
6
27
38

5

votes

0 answers

Does aborting a partial FPGA reconfiguration possibly result in an undefined state?

I'm working on a reconfiguration controller for a reconfigurable CPU. One of the features I tried to implement is to handle CRC errors properly, and also to allow for aborts during reconfiguration. I am using a Virtex7 board and as described in…

fpga xilinx virtex

asked Jul 11 '16 at 10:36

rtur

165
9

4

votes

1 answer

How to use an OLED display for an Avnet Virtex4?

I have an Avnet ADS-XLX-V4FX-EVL12-G (Virtex4 Evaluation Board) with OLED display. I used Xilinx EDK 10.1 with Xilinx Platform Studio 10.1 and succeded to upload some basic app to the board (serial communication). Now I would like to use the OLED…

embedded fpga xilinx virtex

asked Mar 30 '09 at 14:33

Ionel Bratianu

836
2
13
26

4

votes

1 answer

Flip-Flop triggered on the edge of two signals

I need a flip flop that reacts on the edges of two different signals. Something like this: if(rising_edge(sig1)) then bit <= '0'; elsif(rising_edge(sig2)) then bit <= '1'; end if; Does such a flip flop exist or is there some other technique…

vhdl xilinx virtex

asked Aug 19 '09 at 18:08

giroy

2,203
6
27
38

3

votes

1 answer

What is it called the threads on the FPGA (Xilinx Virtex 5/7), and how many number of its can be?

What is it called the thread of execution on the FPGA (Xilinx Virtex 5/7), and how many number of its can be theoretically (minimum and maximum)?

multithreading fpga xilinx virtex

asked Oct 05 '13 at 08:50

Alex

12,578
15
99
195

2

votes

1 answer

How do I verify readback data on a Xilinx Virtex 5?

I know it talks about it in the configuration guide, but it seems like a pain to verify it visually. Are there any tools available to automatically verify readback data?

fpga xilinx virtex

asked Apr 03 '15 at 17:19

TravisChambers

526
4
12

2

votes

1 answer

How do I read the status register of a Virtex 5 in a JTAG chain?

I'm working on an XUPV5-LX110T and I'm trying to read the status register over JTAG. I'm getting incorrect data, but I can't see why. I seem to be getting all zeros. I suspect it has to do with the order of the JTAG chain, but I'm not sure how I…

fpga jtag virtex

asked Feb 07 '15 at 00:11

TravisChambers

526
4
12

2

votes

1 answer

Configuring a 7-Series GTXE2 transceiver for Serial-ATA (Gen1/2/3)

Hello this will be an experts questions :) You should be familiar with the following topics Xilinx Multi-Gigabit-Transceivers (MGTs), especially the 7-Series GTX/GTH transceivers (GTXE2_CHANNEL) Serial-ATA Gen1, Gen2 and Gen3, especially…

fpga xilinx sata register-transfer-level virtex

asked Aug 14 '14 at 20:14

Paebbels

15,573
13
70
139

2

votes

2 answers

Make a simple circuit to dissipate power in VHDL

I'm looking for ideas on something simple to write that I can use to measure power. I just need it to make sure that my power measurement is working. I'm using Xilinx ISE 14.1 on a Virtex-6. I'd like a simple circuit to write and to synthesize. So…

vhdl xilinx circuit virtex

asked Aug 17 '12 at 01:43

Stuart

1,733
4
21
34

2

votes

3 answers

Why isn't this VHDL inferring BRAM in XST?

I have an array of vectors that I want to be stored in Block RAM on a Virtex-5 using ISE 13.4. It is 32Kb which should fit in 1 BRAM but it is all being stored in logic. My system uses an AMBA APB bus so I check for a select line and an enable line.…

xilinx synthesis virtex

asked Jun 21 '12 at 02:25

Stuart

1,733
4
21
34

1

vote

1 answer

How can I create multiplier that uses OPMODE[6:4] = 100 OPMODE[3:2] = 10 OPMODE[1:0] = 00?

In DSP48E1 X Y and Z muxes are controlled using OPMODE singal(7 bit input [6:4] bits are selectors for Z mux , [3:2] bits are for Y mux and [1:0] bits are for X mux) . I have written verilog codes for multiplier(for Vivado tool Virtex 7 - DSP48E1)…

verilog vivado synthesis virtex

asked Aug 03 '21 at 18:54

Tatev2919

21
2

1

vote

0 answers

Clock Wizard IP affects Critical Path

I am using Virtex-7 Evaluation board which has 200Mhz clock. My design has a critical path less than 4ns. I am trying to use clock wizard IP to generate 120MHZ clock from the input clock of 200MHz. However, I faced with failing timing after…

fpga vivado virtex

asked Jan 05 '18 at 20:25

Elnaz

21
5

1

vote

1 answer

Reaching clock regions using BUFIO and BUFG

I need to realize a source-synchronous receiver in a Virtex 6 that receives data and a clock from a high speed ADC. For the SERDES Module I need two clocks, that are basically the incoming clock, buffered by BUFIO and BUFR (recommended). I hope my…

buffer vhdl fpga clock virtex

asked Mar 18 '17 at 12:02

ARude

65
1
10

1

vote

1 answer

Xilinx Virtex6 block ram width

I'm confused about Virtex-6 BlockRAM. I want to implement a BRAM with 15 bit address (32,768 words) and 12 bit write and read data per word. When I explore the implemented design, I founded that 12 BlockRAM are used for this. Does this mean each…

fpga xilinx virtex

asked Feb 28 '16 at 11:45

Mohammad

69
10

1

vote

1 answer

Interfacing with Xilinx virtex-5 FPGA board

i have been working with spartan 3e starter kit board for long time. But now i am trying to work with virtex-5 ml505 xc5vlx110t board(ff1136). And the very first problem that I am facing is that xilinx ise 14.7 does not have package of this board(it…

verilog fpga xilinx-ise virtex

asked Nov 22 '15 at 19:07

Utkarsh Jain

57
4

Questions tagged [virtex]