Questions tagged [xilinx]

Xilinx is a major brand of Field Programmable Gate Arrays (FPGA) and CPLDs (Complex Programmable Logic Devices)

Xilinx is known for its fpga devices:

Spartan
Virtex
Kintex
Artix
Zynq Portfolio: System on Chip device along with a FPGA
Versal: 7nm adaptive compute acceleration platform (ACAP)

And the software tools it offers:

Vivado HLS: IP creation using C, C++ and System C
Vivado IP Integrator: create, configure and integrate IPs
System Generator: define, implement and test DSP algorithms
Vitis: embedded software and accelerated applications development
Vitis AI: AI inference stack to run neural networks

With intellectual properties like microblaze soft processor.

Useful links

Website: https://www.xilinx.com
Knowledge base: https://www.xilinx.com/support.html#knowledgebase
Documentation: https://www.xilinx.com/support.html#documentation
Forum: https://forums.xilinx.com
Versal info.

1399 questions

-1

votes

1 answer

file does not exist in VHDL

I want to read from a text file and show it in the ISE environment, I have the code below, but when I run it the error: File does not exist. is created, I have the test.txt file in the folder that the codes sources exist in. What is…

vhdl xilinx xilinx-ise

asked May 02 '16 at 06:59

Sheyda Alizadeh

-1

votes

2 answers

need your help for the following vhdl code in Xilinx tool

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity conv_enc is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; inp : in STD_LOGIC; outp : out …

vhdl xilinx xilinx-ise xilinx-edk

asked Apr 18 '16 at 11:35

haftish

-1

votes

2 answers

ISim Post-Route Simulation ERROR

I was attempting to test a VHDL project with Isim Simulator within ISE. Behavioral simulation works fine while Post-Route produces a lot of errors of this kind: Warning: /X_FF PULSE WIDTH High VIOLATION ON RST; Expected:= 1.794 ns; Observed:=1.369…

vhdl simulation fpga xilinx xilinx-ise

asked Feb 25 '16 at 17:09

Mazzola

-1

votes

1 answer

Yocto fails to boot after adding package

I'm about to build a Linux-Yocto filesystem for Xilinx Zynq platform. Everything runs fine until I added one more package to the rootfs. It doesn't matter what kind of package I'm adding it always fails with: INIT: version 2.88…

linux xilinx yocto recipe bitbake

asked Feb 19 '16 at 16:18

Javerik

-1

votes

1 answer

Multiplier 4-bit with verilog using just full adders

I am trying to write the test bench part but I don't know how to do it. Basically, I want to test out 0x10 or 5x5. I don't if what I have is right. here's a pic to give you some idea of what i am trying to build. it is not this exact one. Here is…

verilog xilinx hdl test-bench

asked Jan 19 '16 at 01:01

CharleBarkely123

-1

votes

1 answer

Error on converting bit files to ace files

I want to convert .bit file to .ace file using the command prompt. I try to create .bat file to do that. But when I execute the command, no files are added to the specified directory. The batch file is named makeace and has this code: @echo off if…

batch-file xilinx xilinx-ise xilinx-edk

asked Oct 25 '15 at 18:05

sepeee

-1

votes

1 answer

Wrong Truth Table for 2 bit comparator using 2 inputs and 3 outputs

I am making a 2 Bit Comparator with 2 inputs and 3 outputs. I wrote the following code in VHDL and when I created schematic using Xilinx, it showed the wrong truth tables and K maps for all of them. Here's my code: library IEEE; use…

vhdl xilinx

asked Aug 16 '15 at 15:34

facebook-100003312828525

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votes

1 answer

Simulation error on vivado: A fatal run-time error was detected. Simulation cannot continue

I have the following error when I try to run a simulation with vivado: A fatal run-time error was detected. Simulation cannot continue. Any idea about the type of the error? Below my testbench: library ieee; use ieee.std_logic_1164.all; use…

vhdl xilinx vivado

asked Jul 13 '15 at 10:44

user3914897

-1

votes

2 answers

How to connect an external sensor to Zynq-7000 module?

I'm currently working on a project to be implemented on a Xilinx Zedboard, using Simulink Embedded Coder methodology. i need to interface an analog sensor (Electret Microphone) with the Zynq,i know that the XADC need to be instanciated in the PL…

simulink xilinx zynq

asked Apr 02 '15 at 14:05

Sami Ben

-1

votes

1 answer

ISIM only simulates until 61.215.000 picoseconds

Despite me setting any interval my simulation only runs that long using the built-in ISIM simulator. Even if I run the simulator, rerun the simulation and/or take small steps it stops there. Is there anything I can do? It started doing it without…

vhdl simulation xilinx

asked Dec 17 '14 at 15:02

Ákos Godó

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votes

1 answer

calculate how many times input is repeated verilog

I'm trying to calculate times in which input x with 8 bits is repeated on every posedge clk. I'm thinking about creating 256b counter to each value of these 8 bit to compare x with it, but I get error when I'm trying to compare each value of these…

verilog xilinx

asked Nov 27 '14 at 22:33

user2014

-1

votes

4 answers

ambiguous clock in event control

I wrote such verilog code in xilinx vivado: module a(input clk, input clk1, output reg [4:0] acc) initial begin acc = 5'd0; end always @ (posedge clk or posedge clk1) begin acc <= acc+1; end endmodule And the error (ambiguous clock in event…

verilog xilinx vivado

asked Nov 26 '14 at 09:32

K2082

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votes

1 answer

How uboot gets loaded

How does the uboot gets loaded for a particular embedded linux device? Is there a program inside the chip that searches for uboot inside the sd card or it is some another concept?

embedded-linux xilinx xilinx-edk

asked Aug 27 '14 at 15:43

harshul jain

-1

votes

1 answer

Place and route timing strategy

This sounds very naive, but i would like your expert comments on the below pseudo-code. Which of the 2 methods below can achieve minimal place & route timing when implemented in hardware. Method:1 control_proc: process(clk) begin if(clk'event…

vhdl fpga xilinx

asked May 21 '14 at 13:22

powernest

-1

votes

1 answer

Implementing the PMod-ALS on the Basys2 Board in VHDL

I'm attempting to use the ALS Pmod with the Basys2 board in VHDL. How would I go about doing so?

vhdl xilinx

asked Mar 10 '14 at 01:51

Macslayer

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