calculate how many times input is repeated verilog

Question

I'm trying to calculate times in which input x with 8 bits is repeated on every posedge clk. I'm thinking about creating 256b counter to each value of these 8 bit to compare x with it, but I get error when I'm trying to compare each value of these counter with each input x on rising edge.

module counter_initial(x);
  input[7:0] x;
  //output [7:0] y;
  //reg [7:0] y;
  //reg [7:0] freq_tst,gap_tst;
  reg [7:0] freq_num;
endmodule

module counter_256(clk,x,out);
  input [7:0] x;
  input clk;
  // input [7:0] in;
  output [7:0] out;
  reg [7:0] out;
  //reg [7:0] freq_tst,gap_tst;
  reg [7:0] k=0;
  // reg [] t=0;

  genvar i;
  generate
    for (i=0;i<256;i=i+1)
    begin
      counter_initial m(i);
      //t=m(i);
    end
  endgenerate

  always @(posedge clk)
  begin
    if(k<256) begin
      if (x==m[i])
      //counter_initial[k]==x
      begin 
        freq_num=freq_num+1; 
      end
      //else
      //begin gap_tst=gap_tst+1; end
      k=k+1;
    end
  end 
endmodule

Answer 1

You don't need an additional module to count. You can use a memory array. Example:

input [WIDTH-1:0] x;

reg [7:0] mem [WIDTH-1:0];
integer i;

always @(posedge clk) begin 
  if (reset) begin
    for (i = 0; i < 2**WIDTH; i = i+1) begin
      mem[i] <= 8'b0;
    end
  end
  else if (mem[x] < 8'd255) begin // cap counting and prevent overflow
    mem[x] <= mem[x] + 1'b1;
  end
end

If you want to use separate modules then pass the clock to it. Example:

module counter (output reg [7:0] count, input increment, clk, reset);
  always @(posedge clk) begin
    if (reset) begin
      count <= 8'b0;
    end
    else if (count < 8'd255) begin // cap counting and prevent overflow
      count <= count + increment;
    end
  end
endmodule

module my_device ( /* ..., */ input [7:0] x, input clk, reset );
/* ... */
genvar i;
generate
for (i=0; i<256; i=i+1) begin
  counter icount( .count(/* ... */), .increment(x==i), .* );
end
endgenerate
/* ... */
endmdoule

Reminder 8'd255 + 1 is 8'd0 because the MSB of 8'd256 is out of range. I capped the counters so the will not overflow and roll back to zero.