need your help for the following vhdl code in Xilinx tool

Question

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity conv_enc is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           inp : in  STD_LOGIC;
           outp : out  STD_LOGIC_VECTOR(3 DOWN TO 0));
end conv_enc;

architecture Behavioral of conv_enc is
begin
 process
 variable ff:std_logic_vector(3 down to 0);
  begin
   wait until rising_edge (clk)
     if rst='1' then
      ff<="0000";
     else
      for i in 2 down to 0 loop
       ff(i)<=ff(i+1);
        end loop;
        ff(3)<=inp;
    end if;
 end process;
 outp(0) <= inp xor ff(1) xor ff(0) ;
 outp(1) <= inp xor ff(3) xor ff(2) xor ff(1) ;
 outp(2) <= inp xor ff(3) xor ff(2) xor ff(1) xor ff(0);
 end Behavioral;

THE ERROR SAYS: HDLParsers:3481 - Library work has no units. Did not save reference file "xst/work/hdllib.ref" for it. PLEASE HELP

You should not use `STD_LOGIC_UNSIGNED` or `STD_LOGIC_ARITH`; your code does not perform any arithmetic, and even if it did, you would use `numeric_std` package for this. — scary_jeff, Apr 18 '16 at 12:56

score 3 · Answer 1 · 2016-04-18T21:50:12.977

While Maria and scary_jeff give partial solutions there are several errors:

You declared a range down to instead of downto in three places.

You missed a semicolon terminating the wait statement in the process.

You attempt to read a variable outside of a process (outside it's scope).

The following is your code correcting these, notably making ff a signal:

library ieee;
use ieee.std_logic_1164.all;
-- use IEEE.STD_LOGIC_ARITH.ALL;
-- use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity conv_enc is
    port (
        clk:   in  std_logic;
        rst:   in  std_logic;
        inp:   in  std_logic;
        outp:  out std_logic_vector(3 downto 0) -- WAS DOWN TO
    );
end entity conv_enc;

architecture behavioral of conv_enc is
     signal ff:   std_logic_vector(3 downto 0); -- variable used outside process
begin
    process
        -- variable ff:   std_logic_vector(3 downto 0);  --  was down to
    begin
        wait until rising_edge (clk);  -- was miaaing terminating semicolon
        if rst = '1' then
            ff <= "0000";
        else
            for i in 2 downto 0 loop   -- was down to
                ff(i) <= ff(i + 1);
            end loop;
            ff(3) <= inp;
        end if;
    end process;

    outp(0) <= inp xor ff(1) xor ff(0);
    outp(1) <= inp xor ff(3) xor ff(2) xor ff(1);
    outp(2) <= inp xor ff(3) xor ff(2) xor ff(1) xor ff(0);

 end architecture behavioral;

Note the unused Synopsys packages are commented out.

Your code then analyzes.

Note there is no assignment to outp(3).

Your convolutionally encoder doesn't look quite right, but that could just be me.

Without a testbench providing stimuli and expected results the functionality can't be validated.

Maria · Answer 2 · 2016-04-18T12:12:01.470

0

The ff(3)<=inp; must be right after the else.

edited Apr 18 '16 at 12:12

answered Apr 18 '16 at 12:06

Maria

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need your help for the following vhdl code in Xilinx tool

2 Answers2