Questions tagged [xilinx]

Xilinx is a major brand of Field Programmable Gate Arrays (FPGA) and CPLDs (Complex Programmable Logic Devices)

Xilinx is known for its fpga devices:

Spartan
Virtex
Kintex
Artix
Zynq Portfolio: System on Chip device along with a FPGA
Versal: 7nm adaptive compute acceleration platform (ACAP)

And the software tools it offers:

Vivado HLS: IP creation using C, C++ and System C
Vivado IP Integrator: create, configure and integrate IPs
System Generator: define, implement and test DSP algorithms
Vitis: embedded software and accelerated applications development
Vitis AI: AI inference stack to run neural networks

With intellectual properties like microblaze soft processor.

Useful links

Website: https://www.xilinx.com
Knowledge base: https://www.xilinx.com/support.html#knowledgebase
Documentation: https://www.xilinx.com/support.html#documentation
Forum: https://forums.xilinx.com
Versal info.

1399 questions

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Transmitting data rate and Receive Window Size

Nowadays, I am making a project relating to protocol communication between 2 FPGA. When I read information about TCP/IP ethernet, the window receive which the amount data that computer can accept. And there are a relationship between Window receive…

networking xilinx xilinx-ise

asked May 27 '18 at 10:31

Tai Chau

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1 answer

Perl Script for Bulk Adding Users to a Group after it Reads from a CSV Line

I'm attempting to bulk add users to a group using a CSV file and I'm running into a few frustrating errors that I can't seem to find online elsewhere: useradd: invalid shell '-d/home/jbower11' --(for all users in the list) Use of uninitialized…

perl ubuntu scripting xilinx

asked Mar 31 '18 at 02:07

studentneedshelp

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2 answers

How to use stringstream in Xilinx SDK?

When trying to add #include which is needed for stringstream, I get several errors, the following included: expected ';' at end of input expected '}' at end of input macro "str" requires 2 arguments, but only 1 given How to enable using…

embedded xilinx xilinx-edk

asked Mar 20 '18 at 16:12

Matan L.

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1 answer

Basys3 board 4-bit counter, I don't know why its not producing bit-stream? Error in implementation

I wanted to make a 4-bit counter on Basys3 board using Vivado. I wrote a code for it in verilog. I am not able to generate the bit stream. I have pasted stopwatch.v module and constraint file. The onboard clock speed of Basys3 is…

verilog xilinx vivado

asked Mar 12 '18 at 16:17

Nipun Pruthi

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1 answer

Vivado 2015.1 VHDL Input/ Output Violation

I am getting through the tutorial of Nexys 4 DDR and I am implementing a simple MUX library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; -- Uncomment the following library declaration if using -- arithmetic…

vhdl xilinx vivado

asked Nov 17 '17 at 10:11

ayo

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1 answer

Custom xilinx zynq board (MYIR) kernel starting hung

I have a custom zynq board(MYC-C7Z010/20 CPU Module) and compile original u-boot+Linux 3.15.0 for it succesfully and it works fine. But I try to update my kernel with this git repository https://github.com/Xilinx/linux-xlnx. I add my board defconfig…

linux-kernel xilinx freeze zynq

asked Oct 22 '17 at 13:52

Mohammad Farahani

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1 answer

How to declare a variable length std_logic_vector signal

I have a std_logic_vector input declared in my program, say number : std_logic_vector(7 downto 0). I want to declare a std_logic_vector type signal whose length goes on increasing till the length of my input 'number'. To be specific, I want a…

vhdl xilinx vivado

asked Jun 16 '17 at 07:17

Veena

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2 answers

VHDL package not compiling

I am new to VHDL and I'm using VIvado 2017.1. I'm trying to use a package to define constants and other such enumerated types to include in multiple models. Right now however, I am unable to use the package in my model. I keep getting Error:…

package vhdl xilinx vivado

asked May 09 '17 at 08:40

user5565748

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1 answer

using packages in vhdl

There are a few modules and a package in VHDL. How will we use the package in the modules. we have already use.work.Package_name.all; but it did not work. And where will we store the package and the modules? Please specify an example path. How to…

vhdl xilinx

asked Mar 28 '17 at 08:38

Ayush Gupta

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votes

1 answer

Error while checking syntax

module mult(a, b, p); input [16:0] a; input [16:0] b; output p; wire [31:0] p; reg i; wire pv; wire bp; assign pv = 32'b0; assign bp = {16'b0,b} ; initial begin for (i = 0; i < 32 ; i = i + 1) begin …

verilog xilinx xilinx-ise

asked Feb 14 '17 at 06:09

prakash Sri

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1 answer

VHDL uart which send 16 chars string

I have to do UART with vhdl on the Xilinx which will send 16 chars string. I wrote such code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.ALL; entity uartByJackob is Port ( CLK, A, B, C : in …

vhdl xilinx

asked Feb 07 '17 at 13:54

Stefan

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1 answer

mem_test.bat file does not execute

I am in the middle of designing a schematic in Xilinx ISE 14.7 core generator and I've run into a little problem which I need help with. I need to run mem_edit.bat file in order to run the memory editor application and create a .coe file. Whenever I…

hardware fpga xilinx

asked Jan 26 '17 at 20:39

Alex

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2 answers

Does the following style of coding makes any difference while synthesis?

I am trying to implement a module in my project for which i need the final value to be stable for a while, hence implemented as below. both of them are showing the same result in simulation. will the tool generate same hardware or different…

verilog xilinx synthesis

asked Nov 24 '16 at 06:10

vlsi_user

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votes

3 answers

Trying to implement a stack in Verilog. What's wrong with the code?

I'm new to Verilog, so please excuse any newbie mistakes. I'm trying to implement a 3 byte stack in verilog. Using R_W to read write (push/pop) and a 2D Array to store the contents of the stack. `timescale 1ns / 1ps module one(R_W,PUSH,POP); …

verilog fpga xilinx hdl

asked Jun 20 '16 at 07:28

gambhirprateek

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1 answer

Array output in verilog

I'm working on a school homework and I'm finding difficulties in outputing an array with values of 1.I used this code,but the simulator keeps filling the signal bar with X integer index = 0; initial begin for(index=0;index<=7;index = index+1) …

arrays for-loop output verilog xilinx

asked May 14 '16 at 21:28

Dragos Alexe

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