Simulation error on vivado: A fatal run-time error was detected. Simulation cannot continue

Question

I have the following error when I try to run a simulation with vivado:

A fatal run-time error was detected. Simulation cannot continue.

Any idea about the type of the error? Below my testbench:

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-------------------------------------------------------------------------------

entity tb_processing_unit is

end tb_processing_unit;



architecture behavioral of tb_processing_unit is

  component processing_unit is
    port (bus_clk : in  std_logic;
          rst     : in  std_logic;
          enable  : in  std_logic;
          GPIO    : in  std_logic_vector (7 downto 0);
          din_0   : in  std_logic_vector (7 downto 0);
          din_1   : in  std_logic_vector (7 downto 0);
          din_2   : in  std_logic_vector (7 downto 0);
          o_data  : out std_logic_vector (7 downto 0);
          o_wr_en : out std_logic;
          p_data  : out std_logic_vector (31 downto 0);
          p_wr_en : out std_logic;
          p_full  : in  std_logic
          );
  end component;

-- the size of the frames to be processed
  constant FRAME_HEIGHT : integer := 480;
  constant FRAME_WIDTH  : integer := 854;


  signal clk         : std_logic := '0';
  signal reset       : std_logic := '0';
  signal enable_sig  : std_logic;
  signal din_0_sig   : std_logic_vector (7 downto 0);
  signal din_1_sig   : std_logic_vector (7 downto 0);
  signal din_2_sig   : std_logic_vector (7 downto 0);
  signal o_data_sig  : std_logic_vector (7 downto 0);
  signal o_wr_en_sig : std_logic;
  signal GPIO        : std_logic_vector (7 downto 0);
  signal prof_data   : std_logic_vector (31 downto 0);
  signal prof_wren   : std_logic;
  signal prof_full   : std_logic;

-- signals as expected 
  signal Gx_exp, Gy_exp : unsigned (9 downto 0)         := (others => '0');
  signal o_dat_exp      : std_logic_vector (7 downto 0) := (others => '0');


begin

-- Instantiate the Unit Under Test (UUT)
  uut : processing_unit
    port map (enable  => enable_sig,
              din_0   => din_0_sig,
              din_1   => din_1_sig,
              din_2   => din_2_sig,
              o_data  => o_data_sig,
              o_wr_en => o_wr_en_sig,
              rst     => reset,
              bus_clk => clk,
              GPIO    => GPIO,
              p_data  => prof_data,
              p_wr_en => prof_wren,
              p_full  => prof_full
              );

-- generate a clock with 100 ns period
  clkg : process
  begin
    wait for 50 ns;
    clk <= not clk;
  end process;

-- generate some testpatterns 
  tb : process
  begin
    prof_full  <= '0';
    din_0_sig  <= X"00";
    din_1_sig  <= X"00";
    din_2_sig  <= X"00";
    GPIO       <= "00000111";
    enable_sig <= '0';

    wait for 200 ns;

    -- we reset the fsm
    reset <= '1';
    wait for 100 ns;
    reset <= '0';

    -- no we enable the unit
    enable_sig <= '1';

    -- have to wait until the processing unit is
    -- really outputting calculated values from the sobel
    -- filter (it waits 
    enable_sig <= '1';

--  FOR i in 1 TO (2*FRAME_WIDTH+2) LOOP
    wait for (2*FRAME_WIDTH+2) * 100 ns;

    din_0_sig  <= X"33";
    din_1_sig  <= X"40";
    din_2_sig  <= X"43";
    wait for 100 ns;
    din_0_sig  <= X"F5";
    din_1_sig  <= X"9B";
    din_2_sig  <= X"59";
    wait for 100 ns;
    din_0_sig  <= X"C0";
    din_1_sig  <= X"C6";
    din_2_sig  <= X"B2";
    wait for 100 ns;
    din_0_sig  <= X"02";
    din_1_sig  <= X"0D";
    din_2_sig  <= X"A0";
    wait for 100 ns;
    din_0_sig  <= X"D4";
    din_1_sig  <= X"DC";
    din_2_sig  <= X"22";
    wait for 100 ns;
    din_0_sig  <= X"41";
    din_1_sig  <= X"FC";
    din_2_sig  <= X"FF";
    wait for 100 ns;
    din_0_sig  <= X"DB";
    din_1_sig  <= X"39";
    din_2_sig  <= X"4E";
    wait for 100 ns;
    din_0_sig  <= X"85";
    din_1_sig  <= X"43";
    din_2_sig  <= X"7D";
    wait for 100 ns;
    din_0_sig  <= X"81";
    din_1_sig  <= X"57";
    din_2_sig  <= X"29";
    wait for 100 ns;
    din_0_sig  <= X"A4";
    din_1_sig  <= X"C5";
    din_2_sig  <= X"73";
    wait for 100 ns;
    enable_sig <= '1';
    wait for 300 ns;

    wait;                               -- will wait forever
  end process;

  gxy_exp : process
  begin
    wait for ((2*FRAME_WIDTH+6)*100 ns + 50 ns);
    Gx_exp <= B"00" & X"1e";
    Gy_exp <= B"00" & X"02";
    wait for 100 ns;
    Gx_exp <= B"00" & X"50";
    Gy_exp <= B"00" & X"0f";
    wait for 100 ns;
    Gx_exp <= B"00" & X"41";
    Gy_exp <= B"00" & X"26";
    wait for 100 ns;
    Gx_exp <= B"00" & X"39";
    Gy_exp <= B"00" & X"03";
    wait for 100 ns;
    Gx_exp <= B"00" & X"0a";
    Gy_exp <= B"00" & X"0f";
    wait for 100 ns;
    Gx_exp <= B"00" & X"4f";
    Gy_exp <= B"00" & X"01";
    wait for 100 ns;
    Gx_exp <= B"00" & X"22";
    Gy_exp <= B"00" & X"07";
    wait for 100 ns;
    Gx_exp <= B"00" & X"36";
    Gy_exp <= B"00" & X"0c";
    wait for 100 ns;
    Gx_exp <= B"00" & X"08";
    Gy_exp <= B"00" & X"1e";
    wait for 100 ns;
    Gx_exp <= B"00" & X"23";
    Gy_exp <= B"00" & X"1d";
    wait for 100 ns;
    Gx_exp <= B"00" & X"29";
    Gy_exp <= B"00" & X"1d";
    wait for 100 ns;
    Gx_exp <= B"00" & X"00";
    Gy_exp <= B"00" & X"18";
    wait;                               -- wait forever
  end process;

  od_exp : process
  begin
    wait for 650 ns;
    o_dat_exp <= X"80";
    wait for (2*FRAME_WIDTH+2) * 100 ns;
    o_dat_exp <= X"ff";
    wait for 200 ns;
    o_dat_exp <= X"00";
    wait for 100 ns;
    o_dat_exp <= X"ff";
    wait for 600 ns;
    o_dat_exp <= X"00";
    wait;                               -- wait forever
  end process;


end behavioral;

The error appears when I try to run the simulation

It's probably because of `FATAL_ERROR: Iteration limit is reached` error, but I can't confirm that and help without the code. — Qiu, Jul 13 '15 at 11:19
Testbench doesn't help without the "processing unit" component. Does it report "FATAL_ERROR: Iteration limit is reached"? If not, something else is the problem. Xilinx ISIM does crash : it may be worth trying a different simulator, such as ghdl. GHDL's compiler is quite strict : be prepared for it to report subtle issues that ISIM won't detect but will crash on anyway. https://sourceforge.net/projects/ghdl-updates/ — , Jul 13 '15 at 11:33
Your 'tb' isn't particularly helpful by itself. Did you also author the 'uut'? Note that your log will likely show more than one ERROR. Show the complete text of any found in the log as a first step. The only instance of Vivado log file I could find with an ERROR: [Simulator 45-1]... on the web was proceeded by a more informative ERROR message: "ERROR: Slice range direction "to" does not match prefix slice direction "downto"" It's likely telling you there is semantic error in your code, likely in processing_unit. Trust @BrianDrummond on this. — , Jul 13 '15 at 11:39
HI , thank you :D I tried to run the simulation step by step and I found the problem . — user3914897, Jul 13 '15 at 11:55
Consider closing the question or answering it yourself, keeping in mind what makes a good question and answer - describe the problem and what steps you took to solve it. We could note you haven't told us what the problem was either. — , Jul 13 '15 at 12:08

score 1 · Accepted Answer · answered Jul 13 '15 at 12:42

1

it was an overflow problem . I had the following signals

signal Gx, Gy : unsigned (9 downto 0);
signal G : unsigned (9  downto 0 );

I had an error when executing this multiplication

G <= Gx(7 downto 0)*Gx(7 downto 0)+Gy(7 downto 0)*Gy(7 downto 0);

I considered changing the size of G

signal G : unsigned (15  downto 0 );

Now it's working

answered Jul 13 '15 at 12:42

user3914897

115
2
4
11

The result length of `unsigned(a) * unsigned(b)` is defined as length of a plus length of b. So 8 + 8 -> 16 bits are required for `G`. – Paebbels Jul 13 '15 at 12:59
1

Ah, I believe this would have been caught by a decent simulator. However, Xilinx ISE Simulator runs by default with range checks off! There is a setting (look at "Process Properties/Advanced" in ISE, may have moved in Vivado) to turn them on ... enable it, and the simulator may correctly diagnose the problem. – Jul 14 '15 at 10:41

Simulation error on vivado: A fatal run-time error was detected. Simulation cannot continue

1 Answers1