Multiplier 4-bit with verilog using just full adders

Question

I am trying to write the test bench part but I don't know how to do it. Basically, I want to test out 0x10 or 5x5. I don't if what I have is right.

here's a pic to give you some idea of what i am trying to build. it is not this exact one.

Here is the full adder:

module FA(input a,input b,input cin,output s,output cout);
wire z1,z2,z3;
xor(z1,a,b);
xor(s,z1,cin);
and(z2,z1,cin);
and(z3,a,b);
or(cout,z2,z3);
endmodule

Here is the multiplier:

module multiplier(m0,m1,m2,m3,p);
input[7:0] m0,m1,m2,m3;
output[7:0]p;
wire[11:1]w; // wire
wire[6:1]o; // outputs for the FA
// first part of the diagram
FA stage1(p[1],w[1],m0[1],m1[1]);
FA stage2(o[1],w[2],m0[2],m1[2],m2[2]);
FA stage3(o[2],w[3],m1[3],m2[3],m3[3]);
FA stage4(o[3],w[4],m0[4],m1[4],m2[4]);
// second part of the diagram
FA stage5(p[2],o[1],w[1],w[5]);
FA stage6(o[4],o[2],w[2],w[6],m0[3]);
FA stage7(o[5],o[3],w[3],w[6],w[7]);
FA stage8(o[6],m0[5],m1[5],w[4],w[8]);
// third part of the diagram
FA stage9(p[3],o[4],w[5],w[9]);
FA stage10(p[4],o[5],w[9],w[10]);
FA stage11(p[5],o[6],w[7],w[10],w[11]);
FA stage12(p[6],p[7],w[8],w[11],m0[6]);
endmodule

Here is my test bench:

   module sim();       
   reg [7:0]m0,m1,m2,m3;       
   wire [7:0]p;       
   multiplier uut(.m0(m0),.m1(m1),.m2(m2),.m3(m3),.p(p));

   initial begin m0=0;m1=0;m2=0;m3=0;
   #1 m0=1;m1=1;m2=0;m3=0;
   #1 m0=0;m1=1;m2=0;m3=1;
   #1 m0=1;m1=1;m2=1;m3=1;
   end 
   endmodule

score 0 · Answer 1 · answered Jan 19 '16 at 02:07

0

Your test bench is good way to start. You may want to add $monitor to print the values of those signals that was changed or maybe you may want to view the wave to see your simulation in action.

module sim();       
reg [7:0]m0,m1,m2,m3;       
wire [7:0]p;       
multiplier uut(.m0(m0),.m1(m1),.m2(m2),.m3(m3),.p(p));

initial begin 
  m0=0;m1=0;m2=0;m3=0;
#1 m0=1;m1=1;m2=0;m3=0;
#1 m0=0;m1=1;m2=0;m3=1;
#1 m0=1;m1=1;m2=1;m3=1;
end 

initial begin
  $monitor("m0: %0d m1: %0d m2: %0d m3: %0d p: %0d", m0, m1, m2, m3, p);
end

// you need to check your simulator documentation on how to dump the wave form
initial begin
  $dumpfile("dump.vcd"); $dumpvars;
end
endmodule

You might need to add connections to the following instances wherein the number of ports does not match with the number of ports of your FA module:

FA stage1(p[1],w[1],m0[1],m1[1]);
FA stage5(p[2],o[1],w[1],w[5]);
FA stage9(p[3],o[4],w[5],w[9]);
FA stage10(p[4],o[5],w[9],w[10]);

Another way to check the functionality of your multiplier is to create a reference model then compare it with the output, this way you could send as many inputs as you want while waiting for the result (pass/fail).

answered Jan 19 '16 at 02:07

e19293001

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For the additional connections that I am suppose to add, it is suppose to be a zero. How do I add a zero value port? – CharleBarkely123 Jan 19 '16 at 02:19
also when I run the simulation, the result I get for p is always z. – CharleBarkely123 Jan 19 '16 at 02:20
Just put a zero on it. Something like: `FA stage1(p[1],w[1],m0[1],m1[1],1'b0);` – e19293001 Jan 19 '16 at 02:33
i tried that. this is the error i get "actual bit length 32 differs from formal bit length 1 for port cout" – CharleBarkely123 Jan 19 '16 at 02:35
Edited my comment. Should add `1'b0`. – e19293001 Jan 19 '16 at 02:35
now i am getting this message "illegal output port connection to cout" for the ones I change. – CharleBarkely123 Jan 19 '16 at 02:46
Yes that will create an error since I've assigned a constant to the output. Don't worry. You'll get used to fixing the errors eventually. Try this instead: `FA stage1(1'b0,p[1],w[1],m0[1],m1[1]);` – e19293001 Jan 19 '16 at 02:49
ohh i see now. That works now. How do I multiply 10x5 or 5x6? I get z for the output "p". – CharleBarkely123 Jan 19 '16 at 03:01
`'z` values means that it is an open wire or high impedance. Try to trace and check your connections. – e19293001 Jan 19 '16 at 03:17
if I look at the simulation wave and leave the radix to default it shows zzzzzz1 or zzzzzz0. but if I change it to radix unsigned decimal it becomes "Z". – CharleBarkely123 Jan 19 '16 at 03:37
Alright I looked at the warnings and I am getting alot of these messages" WARNING: [Synth 8-3331] design multiplier has unconnected port m0[7] WARNING: [Synth 8-3331] design multiplier has unconnected port m1[7]". – CharleBarkely123 Jan 19 '16 at 03:47
I also have this warning "Net o in module/entity multiplier does not have driver." – CharleBarkely123 Jan 19 '16 at 03:50
Any reason why you declared `wire[11:1]w;`? IMHO, this is supposed to be `wire[10:0]w;` to make it easier to read and debug. The same with `wire[6:1]o;`. – e19293001 Jan 19 '16 at 04:05
You're getting closer. Just verify your connections. – e19293001 Jan 19 '16 at 04:08
i can't seem to find a mistake. Do you see anything wrong? – CharleBarkely123 Jan 19 '16 at 04:46
From your module declaration: `module FA(input a,input b,input cin,output s,output cout);` And your instantiation: `FA stage1(p[1],w[1],m0[1],m1[1]);` You've connected `p[1]` as your input when supposed to be this should be an output. – e19293001 Jan 19 '16 at 05:08
how would I connect it as an input? I really thought i was doing right. – CharleBarkely123 Jan 19 '16 at 05:26
something like this: `FA stage1(.a(m0[1]),.b(m1[1]),.cin(1'b0),.cout(w[1]),.s(p[1]));` but take note, I'm not sure on its functionality but this is how you can make sure your ports are connected properly. – e19293001 Jan 19 '16 at 05:49
The order of your port should match correctly if you don't want to use a connect-by-name syntax. – e19293001 Jan 19 '16 at 05:55
do I do that for all of the FA stages? – CharleBarkely123 Jan 19 '16 at 06:06

Multiplier 4-bit with verilog using just full adders

1 Answers1