Place and route timing strategy

Question

This sounds very naive, but i would like your expert comments on the below pseudo-code. Which of the 2 methods below can achieve minimal place & route timing when implemented in hardware.

Method:1

control_proc: process(clk)
begin
    if(clk'event and clk=='1') then
        if sig_delay == 1 then
            sig_ctrl <= '1';
        else
            sig_ctrl <= '0';
        end if;

    end if;
end process


delay_proc: process(clk)
begin
    if(clk'event and clk=='1') then
        if <some-condition> then
            sig_delay <= '1';
        else
            sig_delay <= '0';
        end if;
    end if;
end process

Method:2

control_single_proc: process(clk)
begin
    if(clk'event and clk=='1') then
        if <some-condition> then
            sig_delay <= '1';
        else
            sig_delay <= '0';
        end if;

        if sig_delay == 1 then
            sig_ctrl <= '1';
        else
            sig_ctrl <= '0';
        end if;

    end if;
end process

Note: sig_ctrl is used as a CE (chip enable) for another component in the hierarchy, which is kind of bit serialiser.

score 0 · Answer 1 · answered May 21 '14 at 13:30

Your two methods are equivalent. Any good synthesis tool will be able to perform the same optimisations on both cases.

The sorts of things that might prevent a synthesis tool from optimising logically equivalent hardware are entity hierarchy / design partition boundaries, however most tools flatten the netlist before optimisation anyway.

Method 2 may perform marginally better in simulation since there are fewer processes to schedule.

Place and route timing strategy

1 Answers1