Questions tagged [xilinx]

Xilinx is a major brand of Field Programmable Gate Arrays (FPGA) and CPLDs (Complex Programmable Logic Devices)

Xilinx is known for its fpga devices:

Spartan
Virtex
Kintex
Artix
Zynq Portfolio: System on Chip device along with a FPGA
Versal: 7nm adaptive compute acceleration platform (ACAP)

And the software tools it offers:

Vivado HLS: IP creation using C, C++ and System C
Vivado IP Integrator: create, configure and integrate IPs
System Generator: define, implement and test DSP algorithms
Vitis: embedded software and accelerated applications development
Vitis AI: AI inference stack to run neural networks

With intellectual properties like microblaze soft processor.

Useful links

Website: https://www.xilinx.com
Knowledge base: https://www.xilinx.com/support.html#knowledgebase
Documentation: https://www.xilinx.com/support.html#documentation
Forum: https://forums.xilinx.com
Versal info.

1399 questions

-1

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3 answers

BCD and 7segment decoder show strange result

I'm trying to create connection from BCD to 7-segment decoder. When I press button UP_* or DOWN_*, it should counting up or counting down. But my simulation only displays 0000001 even when I press button UP or DOWN. BCD module code: module…

verilog xilinx system-verilog bcd

asked Dec 18 '13 at 04:33

user3110542

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votes

1 answer

Icarus produces different results than Silos

I am recieving some strange results when trying to compile and simulate a Verilog module and stimulus. If I simulate it in Silos, the code functions as expected. If I simulate it in Icarus (iverlog and vvp) the time differs from Silos(the starting…

verilog fpga xilinx hdl icarus

asked Nov 28 '13 at 20:44

dannyn382

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votes

2 answers

How to run an Arduino project on an FPGA

I have an Arduino project and I want to run it on an FPGA (I prefer a Spartan Board), but i am not familiar with a method doing something like that. Can anyone help me?

arduino fpga xilinx spartan

asked Nov 27 '13 at 10:22

an an

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votes

1 answer

How to get the on-chip temperature of Xilinx Virtex-5 FPGA chip?

I'm trying to do an experiment to see how different on-chip temperatures affect the frequency of ring oscillator. I know that as the temperature increases, the frequency of the ring oscillator also decreases. But I don't know how much it will…

fpga xilinx temperature virtex

asked Nov 04 '13 at 04:49

abc

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votes

1 answer

Unexpected warnings in Xilinx

In the following code, I am storing the history of buttons player 1 and player 2 pressed. The code compiles without errors but has warnings. I am unable to solve these warnings. I am posting the code here. module…

verilog xilinx

asked May 15 '13 at 04:15

Naruto

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39

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1 answer

template error in Xilinx

I have written a program in xilinx, this code compiles fine in ModelSim but I get this error when I compile it in xilinx. ERROR:Xst:899 - line 78: The logic for does not match a known FF or Latch template. The description style you are…

verilog xilinx

asked Mar 02 '13 at 13:51

James Aflred

-1

votes

1 answer

injecting a build tool into eclipse cdt

I would like to convert my file into .h and then run the build. How do I do that (particularly, in Xilinx SDK 12.4, which says that it is eclipse Version: 3.5.1.R35x and cdt Version: 6.0.0.201005121341)?

build-automation eclipse-cdt auto-generate xilinx prebuild

asked Nov 14 '12 at 12:18

Val

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votes

2 answers

Xilinx Microblaze Structure padding/Packing

I have two structures : Struct _size1 { union{ short a; struct { char b; char c; }d; struct { char x; char y; …

c++ c gcc xilinx microblaze

asked Aug 06 '12 at 18:04

microb

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votes

0 answers

How to achieve nanosecond precision timestamps obtained from Xilinx's Solarflare network card within TCP options?

I'm working on a project that requires obtaining timestamps with nanosecond precision from Xilinx's Solarflare network card within the TCP options of the packets. I've been researching how to achieve this, but I'm unsure about the feasibility and…

tcp timestamp xilinx openonload

asked Aug 25 '23 at 09:05

İbrahimErtürk

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votes

1 answer

Need help in converting verilog module without input & output ports into synthesizable. Because module without input/output ports is not synthesizable

I created a verilog module for my project, and getting the expected output (but it doesn't has a testbench, it takes required input data by reading a .txt file using $readmemh) But a module without input or output ports cant be synthesized. Need to…

image verilog system-verilog xilinx hdl

asked May 27 '23 at 20:06

Sunil.B

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votes

1 answer

How to correct crop image using FFMPEG&XILINX

I use AWS vt1 with Xilinx SDK and FFMPEG. All from the AWS box with pre-built SDK and so on. I need to extract frames from fullHD but scale it to 480p I stuck with it. Could someone help with the correct options? I have this Python-based code: …

amazon-web-services ffmpeg xilinx

asked May 15 '23 at 12:14

Dmytro

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votes

2 answers

What is the difference in load and move in assembly code?

Beginner at assembly code but I'm a bit confused between the usage of move and load, being: move ra rd load ra rd load ra (rd) from what I've read, move ra rd copies the value from RD to RA, load ra rd copies the value in RD from memory to RA,…

assembly fpga xilinx instruction-set

asked Aug 09 '22 at 07:58

rabbitfufu

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votes

1 answer

How do you download a program off of a Nexys Video A7 FPGA?

I am new to the world of FPGAs besides a course in undergrad using an Altera training board, but I've recently been assigned to do some work with a Xilinx Nexys Video A7 FPGA. Since this project involves updating firmware, my first task is to…

fpga xilinx

asked Apr 29 '22 at 12:03

tyler_bowlcut

-2

votes

1 answer

How do I rewrite this VHDL code to prevent latches?

architecture Behavioral of REGISTERS is type REG_FILE_TYPE is array(0 to 15) of STD_LOGIC_VECTOR(15 downto 0); signal REG_ARRAY : REG_FILE_TYPE:= (others => X"0000"); begin process(WRITE_ENABLE,REG_CLOCK) is begin case (WRITE_ENABLE) is …

case vhdl fpga xilinx

asked May 19 '21 at 18:18

SajivGraham

-2

votes

1 answer

How to write exponential function in verilog?

I am beginner,I have to complete a project which uses exponential to calc with piecewise interpolation.

verilog xilinx hdl exponential

asked Jul 13 '20 at 18:07

sai tarun

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