file does not exist in VHDL

Question

I want to read from a text file and show it in the ISE environment, I have the code below, but when I run it the error:

File <ramfile_rd> does not exist.

is created, I have the test.txt file in the folder that the codes sources exist in.

What is the problem?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use std.textio.all ;
--use ieee.std_logic_textio.all;

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

entity rd is

PORT(
 clk : IN   std_logic;
 a   : out  std_logic_vector (7 downto 0)

    );

end rd;

architecture Behavioral of rd is
--type Integerfiletype is file of integer ;

begin


read_from_file : process(clk)
   FILE ramfile_rd : text;
   variable RamFileLine_rd : line;
   variable di: integer;
     begin
       if(clk'event and clk='1') then

           file_open(ramfile_rd,"test.txt", read_mode);
            read (RamFileLine_rd,di);
            readline (ramfile_rd, RamFileLine_rd);
            a<=conv_std_logic_vector(di,8);
        file_close(ramfile_rd);

  end if;
 end process;
end Behavioral;

Did you try an absolute path to your text file? Maybe Xilinx ISE is not searching in your source directory but in your workspace of your ISE project. — michi.b, May 02 '16 at 07:08
no, how should i use an absolute path? where is the ISE project workspace? thank you — Sheyda Alizadeh, May 02 '16 at 07:13
XST is loading files from working directory, which is the xst sub-directory. The best way is to use absolute paths. — Paebbels, May 02 '16 at 07:14
Absolute path example: file_open(ramfile_rd,"C:\my\path\test.txt", read_mode); — michi.b, May 02 '16 at 07:16
Btw: opening and closing a file in every clock cycle is no good idea .... — Paebbels, May 02 '16 at 07:17
the absolute path didn't work, again the same error occurred, are you sure the problem is not from somewhere else? — Sheyda Alizadeh, May 02 '16 at 07:29
Are you sure that your "use std.textio.all ;" works? There is an whitespace between library name and your semicolon. I don't know but maybe this could be a problem to load the library. Without the library it won't work obviously. Here is an example to read files: [http://vhdlguru.blogspot.de/2011/02/file-reading-and-writing-in-vhdl-part-2.html](http://vhdlguru.blogspot.de/2011/02/file-reading-and-writing-in-vhdl-part-2.html) — michi.b, May 02 '16 at 07:36
the space between the semicolon and the library syntax is not an important problem, i think it works because without that i saw others errors that they disappeared by adding the library. actually i just wanted to read an image for the ISE and do some processing on it. — Sheyda Alizadeh, May 02 '16 at 07:41

score 0 · Answer 1 · answered May 20 '16 at 09:25

Heyyyy!!

Try to write the code as a testbench, it will simulate. And insert some integer value in test.txt file.while simulation u will get the same value as saved in test file.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use std.textio.all;
--use ieee.std_logic_textio.all;

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

entity rd is
--PORT(
----     clk : IN   std_logic;
--     a   : out  std_logic_vector (7 downto 0)
--    );
end rd;

architecture Behavioral of rd is
signal  a : std_logic_vector(7 downto 0):="00000000";

begin

read_from_file : process
FILE ramfile_rd  : text;
variable line_num : line;
variable di       : integer:= 0;

 begin

--  if(clk'event and clk='1') then
     file_open(ramfile_rd ,"D:\test.txt", read_mode);
          while not endfile(ramfile_rd) loop 

          readline (ramfile_rd , line_num);
              read (line_num,di);
          a<=conv_std_logic_vector(di,8);
              wait for 10 ns; 
         end loop;
    file_close(ramfile_rd );

--  end if;
 end process;
 end Behavioral;

file does not exist in VHDL

1 Answers1