Highest Voted 'xilinx-ise' Questions

2

votes

1 answer

How to return a blank line in ISim?

What it currently looks like in my Console Window: at 20 ns: Note: TimerCount: 0 (/TEST_tb/). at 20 ns: Note: TimerTriggerSync: '0' (/TEST_tb/). at 22500 ps: Note: TimerCount: 2 (/TEST_tb/). at 22500 ps: Note: TimerTriggerSync: '0' (/TEST_tb/). at…

vhdl xilinx xilinx-ise

asked Aug 07 '15 at 15:58

VKkaps

159
3
21

2

votes

0 answers

For loop is generating wrong values within testbench process?

I want to return values of A,B, and Y at time values 7.5 ns, 15 ns, 22.5 ns, etc during my simulation. Below is the code I've implemented thus far (for the for loop). Mathemitically it makes sense, but it's returning values at times 7.5 ns, 30 ns,…

vhdl xilinx xilinx-ise

asked Jul 29 '15 at 17:57

user5153260

23
3

2

votes

1 answer

How to create a list of Tcl commands in a text file and then run it in ISim?

Seems a lot more convenient than typing each one individually every time. This link was very unclear to me: http://sagekingthegreat.blogspot.com/2013/08/how-to-execute-tcl-script-in-xilinx.html Sample Code: #Sample Script: restart run 20 ns…

vhdl xilinx xilinx-ise

asked Jul 24 '15 at 19:56

VKkaps

159
3
21

2

votes

1 answer

Xilinx ISE: Should I be concerned about warning Xst:653?

I never mention anything related to GND_3_o or PWR_3_o in my code. What are these signals, should I be concerned about these warnings related to them, and if so, how can I fix them? WARNING:Xst:653 - Signal is used but never assigned. This…

vhdl fpga xilinx-ise

asked Jul 09 '15 at 18:35

Eugene Wu

61
8

2

votes

1 answer

Using C programming to call VHDL implementation

I'm thinking about writing a C function which basically passes an array/vector of real numbers to a VHDL implementation as an argument and the VHDL code does some computation using the array in a FPGA and returns the result back to the C function.…

c vhdl fpga xilinx xilinx-ise

asked Jun 18 '15 at 22:07

Josh

363
3
16

2

votes

1 answer

Any example useage of a BSCANE2 primitive in Xilinx 7 series? (using the JTAG port to configure user design)

I've looked over the info on BSCANE2 in http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf (pg 169 7 Series FPGA Configuration Guide) and I can't quite figure out how to use it based on that descriptions. I want to be…

fpga xilinx jtag xilinx-ise

asked Jun 02 '15 at 21:02

aneccodeal

8,531
7
45
74

2

votes

0 answers

control icap in Partial Reconfiguration

I'm going to implement partial reconfiguration on virtex5 Xilinx Board. I've written 3 modules(top module and up-counter and down-counter) and created bit streams by Plan-ahead.The result is shown by 2 LEDs(up or down count). My problem is how to…

vhdl xilinx-ise microblaze xilinx-edk

asked May 20 '15 at 06:58

nasir khani

37
2

2

votes

1 answer

Sensitivity list error

I want to compute sum of elements of an array. Elements of the array are assigned on each clock rising edge (sequentially). I don't want to get the sum of elements on the next clock rising edge, So the design of sum must be combinational. I can get…

verilog xilinx-ise

asked Apr 21 '15 at 07:46

Amir

507
3
12

2

votes

1 answer

How to properly read device DNA from Xilinx FPGAs using Impact batch commands?

I'm trying to read a Xilinx Spartan 3AN FPGA's 57-bit device DNA using Impact's batch command shell (ISE v14.6) and using the following command line call: impact -batch file.txt The contents of file.txt are: setMode -bscan setCable -p auto addDevice…

fpga xilinx xilinx-ise spartan

asked Mar 30 '15 at 07:41

Ryan

46
4

2

votes

1 answer

Xilinx ISE Board, trying to make two clocks (ZYBO FPGA)

In the reference manual for the ZYBO board that I am using, it informs me that I have up to four clocks I can use. However, when I look through the UCF file, I can only find one of them. Considering that the ISE tools might know where it is, I used…

clock timing xilinx-ise

asked Mar 27 '15 at 20:01

Tropical_Peach

117
11

2

votes

2 answers

Xst:647 Warnings during Synthesis of Shift6 with Top module

I had written the VHDL code for the Arithmetic shift by 6. Code is working fine. But when I am using it as component in my top module the input b6 has some bits that are not used. So it gives Warning during synthesis that Xst:647 - Input…

math warnings vhdl shift xilinx-ise

asked Feb 16 '15 at 10:10

Raj

195
4
12

2

votes

2 answers

VHDL: Concatenating 2 vectors - What is the resulting vector direction?

Thesis: Xilinx XST reverses the direction of vectors after concatenating these. I have a SATAController and a PicoBlaze soft core CPU. This CPU uses a register interface + cross-clocking to read/write test data. The CPU writes to six 8-bit…

vhdl xilinx-ise

asked Feb 11 '15 at 00:59

Paebbels

15,573
13
70
139

2

votes

1 answer

Running Xilinx Command line Tools - XST does not work

I'm currently working on a project that students can hand in their xilinx projects via e-mail and i will Synthesis, Place and Route and generate a bitstream which then should be uploaded to an FPGA. So first things first. I installed the ISE Tools…

bash xilinx xilinx-ise xilinx-edk

asked Jan 05 '15 at 09:47

nablahero

143
1
13

2

votes

1 answer

for-loops in function

I have some questions about timing in verilog when using a for-loop in a function. How do I estimate the clock cycles needed to execute a function in which a for-loop is operating? And how can I estimate the clock time needed for one for-loop…

verilog xilinx-ise

asked Dec 27 '14 at 21:30

k t

343
5
15

2

votes

1 answer

Verilog Tri-State Issue (Xilinx Spartan 6)

Referring to my earlier question here, I've been utilizing tri-states to work with a common bus. I still appear to have some implementation issues. The tri-states use this type of code: assign io [width-1:0] = (re)?rd_out…

verilog xilinx spartan xilinx-ise

asked Jul 29 '14 at 09:28

Shreyas

667
2
7
20

Questions tagged [xilinx-ise]