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Referring to my earlier question here, I've been utilizing tri-states to work with a common bus. I still appear to have some implementation issues.

The tri-states use this type of code:

assign io [width-1:0] = (re)?rd_out [width-1:0]:{width{1'bz}};

Synthesis and translation goes well. No warnings or errors I wasn't expecting (I was expecting some since this is only a trial run and most of the components don't do anything and will hence be left unconnected). But when I actually try to implement it, all busses (there are three) output a 1111111111111111, or a -1, as converted by my binary to BCD converter. I checked if it really the case by instructing the control matrix to halt if the instruction received on the bus is -1, and it did halt.

The warning I receive for the tri-state being converted to logic is:

Xst:2040 - Unit Neptune_I: 16 multi-source signals are replaced by logic (pull-up yes)

Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes):

And so on. Neptune_I is the top module, and I believe the multi-source signals it's referring to are the busses.

I have a doubt whether the pull-up yes is the root of this problem. Is it simply pulling everything up, causing it to be -1 all the time? But this does not make sense to me, because when the tri-state is activated, the signal should be controlled by whatever entity it is supposed to be controlled by.

I would like to take the time to replace the code with logic instead of the tri-states, but I'm unsure how to proceed.

Any help would be appreciated.

Community
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Shreyas
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1 Answers1

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Are these signals going off-chip? Or are they internal to your FPGA? If the answer is the latter, you need to change your code. Modern FPGAs (like Spartan 6) no longer support internal tri-state buffers. They only exist for off-chip signals.

You need to write all of you internal code to avoid tri-state buffers. Create dedicated paths between components, no bidirectional interfaces.

Russell
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  • That would be absolutely awful! I did have one design like that, but I chose to rewrite the entire thing to get it to use bidirectional interfaces since it makes it much more useful. – Shreyas Jul 29 '14 at 14:55
  • Wait, I'm suggesting *not* using bidirectional interfaces. – Russell Jul 29 '14 at 15:05
  • The entire design uses three common busses! It's based on the Magic-I architecture. Look here: http://www.homebrewcpu.com/Magic1.pdf Page 7! – Shreyas Jul 29 '14 at 15:42
  • Wow that's old. Good luck with your design. Using bidirectional interfaces will make things much harder for you. Also you will never be able to tri-state your internal buses. But if you really want to use that architecture then you'll have to figure out something. It wouldn't be my choice. – Russell Jul 29 '14 at 16:33
  • I believe that design was made is 2001. Well a little while of brainstorming later, I have found an architecture that would fit, and would be simpler to code. Third time's the charm. Thanks anyway! – Shreyas Jul 29 '14 at 16:34
  • Ended up coding a completely different architecture. And I'm glad I did! – Shreyas Jul 30 '14 at 21:03