Xst:647 Warnings during Synthesis of Shift6 with Top module

Question

I had written the VHDL code for the Arithmetic shift by 6. Code is working fine. But when I am using it as component in my top module the input b6 has some bits that are not used. So it gives Warning during synthesis that

        Xst:647 - Input <b6<9...14>> is never used.

And during the ASIC implementation it gives warning that

        O6(0),O(1)...O(5) is connected to same logic(ground).

Does this Warnings affects the power of my top module during performance? Can I avoid these warnings? The Code for the Arithmetic Shift 6 is as below.

 entity shift6 is 
    Port ( 
           b6 : in  STD_LOGIC_VECTOR(15 downto 0);
           o6 : out  STD_LOGIC_VECTOR(15 downto 0));
   end shift6;

architecture Behavioral of shift6 is

begin
process(b6) 
begin
   o6(15)<=b6(15);
   o6(14 downto 6)<=b6(8 downto 0);
   o6(0)<='0';
   o6(1)<='0';
   o6(2)<='0';
   o6(3)<='0';
   o6(4)<='0';
   o6(5)<='0';
end process;

end Behavioral;

Just to follow up Brian's answer. Trimming logic is a normal part of the synthesis process. The synthesizer, however, doesn't know what is and isn't supposed to be trimmed away so it issues these warnings to let you know what is going on in case a design error results in removing too much. — Kevin Thibedeau, Feb 16 '15 at 17:01

score 4 · Answer 1 · edited May 23 '17 at 11:50

No, they don't affect this design, and Xilinx's own IP typically generates hundreds of such warnings, so a warning doesn't usually mean a broken design.

Given the code you posted, it's obvious to you already that these bits are unused and can be trimmed out of the circuit, the warning just confirms that.

Errors must be fixed, warnings usually don't matter.

On a more complex design it's worth skimming through the list of warnings in case a mistake has caused the entire design to be trimmed or pay more attention if it appears not to work in hardware, but it's not normally worth extensive re-writing to avoid some warnings, as long as you have already verified the design works correctly in a simulator.

Paebbels · Answer 2 · 2015-02-17T10:22:54.220

In extension to Brian's answer.

Most XST warnings are non-critical, but some are. For example the 'used but never assigned' or the 'latch found' warning. Some other warnings are acceptable for synthesis but can become fatal in later steps, e.g. 'blackbox found' if a netlist file (*.ngc) is missing.

Here is a list of critical warnings that should be solved for a proper design:

HDLCompiler - WarningIDs 89, 92, 321, 634, 797, 871
Xst - WarningIDs 653, 737, 1415, 2935, 3210

I wrote a script to scan the synthesis report (*.syr) for these warnings and IDs. Unfortunately, this script has some bugs, so I won't publish it at the moment. Maybe your are faster in implementing such a scanner for critical warnings.

Xst:647 Warnings during Synthesis of Shift6 with Top module

2 Answers2