In the reference manual for the ZYBO board that I am using, it informs me that I have up to four clocks I can use. However, when I look through the UCF file, I can only find one of them.
Considering that the ISE tools might know where it is, I used the Timing Analyzer to try to get the system to generate a pin LOC that I could use, this was a fialure though.
Then I had the idea to use the PlanAhead tools to try and see if the tools would again generate a UCF file with the needed clock pin locations. Again this failed.
Have I misunderstood the manual? Is there only one clock pin available to me?
Here is the excerpt in question (12 Clock Sources):
The ZYBO provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the PS subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 Mbps). The ZYBO Base System Design configures the PS to work properly with this input clock, and should be used as a reference when creating custom designs.
The PS has a dedicated PLL capable of generating up to four reference clocks, each with settable frequencies, that can be used to clock custom logic implemented in the PL. Additionally, The ZYBO provides an external 125 MHz reference clock directly to pin L16 of the PL. The external reference clock allows the PL to be used completely in dependently of the PS, which can be useful for simple applications that do not require the processor.
The PL of the Zynq-Z7010 also includes two MMCM’s and two PLL’s that can be used to generate clocks with precise frequencies and phase relationships. Any of the four PS reference clocks or the 125 MHz external reference clock can be used as an input to the MMCMs and PLLs. For a full description of the capabilities of the Zynq PL clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” available from Xilinx.
Figure 13 outlines the clocking scheme used on the ZYBO. Note that the reference clock output from the Ethernet PHY is used as the 125 MHz reference clock to the PL, in order to cut the cost of including a dedicated oscillator for this purpose. Keep in mind that CLK125 will be disabled when the Ethernet PHY (IC1) is held in hardware reset by driving the PHYRSTB signal low.
