Highest Voted 'xilinx-ise' Questions

3

votes

1 answer

VHDL reassigning integer signal does not work according to `report` statement

I have this simple VHDL Code aufg4.vhd: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity aufg4 is Port ( clock : in std_logic ); end aufg4; architecture Behavioral of aufg4 is signal tut_counter : integer range 0 to…

vhdl xilinx-ise

asked Nov 06 '16 at 13:35

goulashsoup

2,639
2
34
60

3

votes

3 answers

Verilog: How to delay an input signal by one clock cycle?

I would like to delay an input signal by one complete clock cycle.I have the code below which basically tries to change the signal at posedge of the clock. However, the test bench shows that it doesn't always delay by 1 cycle.In some cases, it…

verilog clock system-verilog xilinx-ise

asked Oct 14 '16 at 07:01

user3330840

6,143
7
26
39

3

votes

1 answer

Should be 1.001 us equal to 1001 ns in VHDL?

I'm currently writing a test to check whether the type time is synthesized / simulated properly in various FPGA vendor tools. One corner case is the usage of real literals as the abstract literal for time values, e.g.: 1.001 us. The IEEE Std.…

vhdl xilinx-ise quartus vivado

asked Jan 11 '16 at 17:32

Martin Zabel

3,589
3
19
34

3

votes

2 answers

Is there a way to show variables in ISim?

I'm trying to moniter the state of this variable: shared variable Div16 : integer := 0; But I am recieving this error in ISim: ISim does not yet support tracing of VHDL variables. Can you convert the variable to a signal within the testbench…

vhdl xilinx xilinx-ise

asked Aug 19 '15 at 13:58

VKkaps

159
3
21

3

votes

1 answer

how do i initialize a std_logic_vector in VHDL?

i have a std_logic_vector(4096 downto 0) Signal and i want to initialize it like below: architecture Behavioral of test is type ram_type is array(4095 downto 0) of std_logic_vector(15 downto 0); signal ram : ram_type; ram(0) :=…

vhdl hdl xilinx-ise

asked May 18 '15 at 09:41

user3927214

67
2
3
9

3

votes

2 answers

How to change slew constraint for a port from slow to fast?

I am trying to synthesize a code, there is no error but in map report I got this informational message as follows:- INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed…

vhdl xilinx xilinx-ise

asked Apr 21 '15 at 13:06

Arslan

35
7

2

votes

2 answers

Why does my VHDL countdown timer on Nexys3 FPGA board switch between 59 and 68?

I created a 60 second countdown timer in VHDL and connected it to the 7-seg displays on a nexys3 FPGA boar but it doesn't work. This is a project for my college class. I'm not really skilled at VHDL or digital electronics at all, but I've managed to…

vhdl fpga xilinx-ise spartan

asked Jun 01 '23 at 08:56

Goran Orsolic

25
3

2

votes

1 answer

Mix of blocking and non-blocking assignments error

I'm getting this error in my code about blocking and non-blocking assignments. I put initially had some blocking assignments done on initialization but moved them to the initial section. I'm still encountering the issue though, and don't know what…

verilog xilinx-ise

asked Sep 11 '21 at 06:27

bitbytten

101
1
6

2

votes

0 answers

Camera Sensor Driver for ov9281

I am trying to write a bare-metal application to stream images on a VGA monitor using an ov9281 camera. This is my Hardware design. I have used the same design with the ov5640 camera (PCAM). Until now I am able to configure ov5640 and steam data…

camera xilinx device-driver xilinx-ise userspace

asked May 16 '21 at 18:42

Gowri Umesh

21
2

2

votes

2 answers

Xilinx ISE Design Suite 14.7 not installing

I am trying to install Xilinx Design Suite ISE 14.7 Web pack on my Windows 10, but it stucks at 92%. I tried many times but can't figure out the problem. I even downloaded software again but the problem persists. All it says is: Enable WebTalk to…

xilinx-ise

asked Apr 12 '21 at 08:41

user14674875

2

votes

1 answer

How to set a signal at both posedge and negedge of a clock?

I'm trying to implement a controller with the function that sends out the same clock signal as its input clock. But the controller can also halt the output signal if needed. I'm implementing it on Xilinx ISE. My idea is: At the negedge of the input…

verilog hdl xilinx-ise

asked Aug 05 '20 at 22:32

Tommytml

23
4

2

votes

1 answer

Unable to get output in Verilog simulation of digital clock

I want to design a seconds counter, which will count from 0 to 59, using Mod10COunter and Mod6Counter. I am trying to test the output using a testbench. The clock generated is perfect. However, the output is always 'X'. This is the code for the…

verilog simulation clock xilinx-ise

asked May 25 '20 at 01:31

SatyajitG

21
1

2

votes

1 answer

compiling entire Xilinx ISE unisims and XilinxCoreLib libraries (minus secure ip) with GHDL simulator

I was curious if anybody has had any luck compiling the entire Xilinx ISE unisims library for GHDL simulator? I tried to compile just the package file for unisims and it gives me an error. I Was wondering if it will compile completely by…

vhdl xilinx-ise ghdl

asked May 10 '19 at 16:29

Bimo

5,987
2
39
61

2

votes

1 answer

VHDL: When can ports be used as signals?

Please help me understand when ports can be used as signals in VHDL. I am asking this question because I am using ports to move data from one component to another in Xilinx ISim, but the data remains undefined at it's destination. My problems could…

vhdl fpga xilinx-ise

asked Sep 27 '18 at 10:18

Nigel Davies

1,640
1
13
26

2

votes

1 answer

Generate bitstream without vendor specific IDE

What I am trying to achieve is to synthesize very simplistic vhdl to bitstream and test on a proto board. Actually language does not matter. Anyone achieved so far so that you can directly generate bit from any form of code without the requirement…

fpga xilinx xilinx-ise xilinx-edk

asked Jul 18 '18 at 12:00

user10099390

Questions tagged [xilinx-ise]