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I've looked over the info on BSCANE2 in http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf (pg 169 7 Series FPGA Configuration Guide) and I can't quite figure out how to use it based on that descriptions.

I want to be able to use the JTAG port on the KC705 board to shift in some configuration data for our design. I think (based on the description there in the user guide linked above) that the BSCANE2 is what I need to do that... but I really don't understand why all of the pins of the BSCANE2 component seem to have the wrong direction (TDO is an input while all of the other JTAG control sigs like TCK, RESET, TDI are outputs). Initially I had thought that there was an implicit connection from the signals of the JTAG port of the FPGA to the instantiated BSCANE2 component, but that doesn't appear to be the case based on the port directions. I suspect I'm missing some information somewhere and while I have read the docs it's still not clear to me how to actually use the BSCANE2 to do what I'm trying to do.

Any example usage of a BSCANE2 component would be appreciated.

NOTE: the description of the BSCANE2 in the user guide linked above says:

The BSCANE2 primitive allows access between the internal FPGA logic and the JTAG Boundary Scan logic controller. This allows for communication between the internal running design and the dedicated JTAG pins of the FPGA

This sounds exactly like what I need.

aneccodeal
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  • That seems correct to me. For example, clock is an input to the FPGA. That signal is implicitly an input to BSCANE2, to access it inside the FPGA, it has to be an output of the block. The signal clk is from the pin to the logic. An input on the fpga, an output for the block driving internal logic. – Jonathan Drolet Jun 02 '15 at 21:12
  • @JonathanDrolet : Ok, so the TCK, TDI, TMS (etc) inputs to the FPGA are implicit inputs to the BSCANE2 block that are then fed back out of the BSCANE2? So I guess that means if I have a shift register with TDI on the input that TDO is fed with the output of that shift register? – aneccodeal Jun 02 '15 at 21:34
  • Yes, although on modern fpga they can be more than one BSCANE2 instantiated, which are daisy-chained inside the fpga. This is fine by the JTAG standard, each BSCANE2 instantiation act like a virtual physical JTAG device. – Jonathan Drolet Jun 03 '15 at 02:55

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Xilinx offers a 8 bit CPU called PicoBlaze that uses a JTAGLoader module to reconfigure the PicoBlaze's instruction ROM at runtime. The JTAGLoader is provided in VHDL for Spartans and Series-7 devices.

But I think JTAG is not a good protocol for data transfer. Especially the JTAG software API is a mess.

What about UART? Most boards have a USB-UART bridge like CP2103 that supports up to 1 MBoud.

Paebbels
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    The JTAG route doesn't seem too onerous. We can use a program like xc3sprog (http://xc3sprog.sourceforge.net/) to ship the data over from the PC to the KC705 FPGA board via the Platform USB II cable... of course, we'll need to construct our own bit file for this, but that doesn't seem too daunting especially since xc3sprog is open source and we can modify it if need be. The UART route would take more room than the BSCANE2 approach and we could be running low on space soon. – aneccodeal Jun 02 '15 at 21:56
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    The UART should be smaller then JTAG, because BSCANE2 does not implement the shift controller for you. It's just a raw JTAG interface. PicoBlaze comes with a LUT/FF optimized [UART6](https://github.com/Paebbels/PicoBlaze-Library/blob/master/documentation%20(Xilinx)/README%20-%20UART6.txt). That needs only 2x 5 slices and includes 2x 16 byte fifo buffers for RX and TX. This UART supports up to 200 MHz or 20 MBaud. Does xc3sprog support Digilent drivers for newer programmer besides parallel cable IV and Xilinx USB programmer? – Paebbels Jun 02 '15 at 22:12
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    Paebbels: From what I can tell from reading http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf (the advanced JTAG usage section) if you've got one BSCANE2 instantiated and you send the USER1 instruction then the SEL from your BSCANE2 is asserted and if CAPTURE or SHIFT are active then DRCK will toggle with TCK. I can then shift in the data coming in on TDI into a shift register clocked with DRCK - that's pretty much all I need. – aneccodeal Jun 03 '15 at 00:26
  • Paebbels: AFAICT neither xc3prog nor fpgajtag (another free JTAG programmer at: https://github.com/cambridgehackers/fpgajtag ) require any special drivers. They're just sending bytes over the USB port. – aneccodeal Jun 03 '15 at 00:29
  • I had a 2nd look into [JTAGLoader6.vhdl](https://github.com/Paebbels/PicoBlaze-Library/blob/master/vhdl/JTAGLoader6.vhdl). It implements shift registers but it's not as low level as a TAP controller. Can xc3sprog be used in parallel to iMPACT? Currently I'm using iMPACT, ChipScope and JTAGLoader in parallel on one device without connecting and disconnecting the cable if I change the tool. If I remember correctly I had to disconnect ChipScope to use xc3sprog and reconnect it after programming the FPGA. – Paebbels Jun 03 '15 at 07:37
  • There must be drivers because the commonly used FTDI USB chip gets a new firmware upload via udev rules. Without it, it won't speek JTAG. So either they use the original drivers and firmwares or they install there own firmware. – Paebbels Jun 03 '15 at 07:42