Xilinx ISE is the toolchain package for programming Xilinx FPGAs in VHDL and Verilog.
Questions tagged [xilinx-ise]
291 questions
2
votes
1 answer
VHDL - connect switch and LED
I have the Xilinx Spartan6 and next VHDL code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Switches_Leds is
Port (switch_0: in STD_LOGIC;
LED_0 : out STD_LOGIC);
end Switches_Leds;
architecture…
Dcbnvn
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2
votes
1 answer
Why the procedure doesn't see the variable?
I'm using Xilinx ISE to create a VHDL project.
I'm trying to add values to an integer variable.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vending2_mod is
Port ( button1 : in STD_LOGIC;
button2 : in STD_LOGIC;
button3 : in …
Exec
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2
votes
0 answers
JTAG Programming Xilinx Spartan 3an FPGA with CPU in chain
I have problems with programming Xilinx 3an1400 FPGA over JTAG interface.
My custom PCB consists of CPU and FPGA connected in the JTAG chain with CPU on 1-st position and FPGA on second. I can access and program the CPU over JTAG without any…
rhr
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- 2
2
votes
2 answers
Xilinx ISE - Wrong maximum frequency?
I have designed a simple Ripple Carry Adder in ISE and, after having synthesized it for my FPGA, the report says that the "maximum combinational path delay" is about 15 ns.
Then, I designed a Robertson multiplier (a sequential circuit), which…
Alessandro
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2
votes
1 answer
Isim is not testing all bits in test fixture
I am trying to test all possible cases of inputs for my Verilog code. I set it up with for loops.
for(sel = 0;sel < 4;sel=sel+1) begin
for(a = 0;a < 8;a=a+1) begin
for(b = 0;b < 8;b=b+1) begin
…
DarkLink
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- 16
2
votes
1 answer
16-bit adder from 4-bit Carry Look Ahead (CLA) - Cout from Block Generate and Propagate
I'm new to Verilog. Here's what I have done so far and the 4-bit CLA works. However, the 16-bit (using instances of 4-bit CLA) doesn't. The problem is definitely in setting the Cout_itermed (intermediate carries) values from block propagate (BP) and…
user5104026
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2
votes
1 answer
How do I initiate a Xilinx ISE Block Memory from a raw memory dump?
I dumped the RAM from a working device that I want to partially emulate on an FPGA. In Xilinx ISE I used the Core Generator to generate a RAM module.
Now there is an option to initialise the RAM with a COE file.
Unfortunately I can't find any tool…
Pepijn
- 4,145
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2
votes
2 answers
VHDL input forced to ground
I am new to VHDL. I was trying to write code for adder subtractor. One of my input bus for the circuity is connected to ground after synthesis. I am using Xilinx ISE 14.2 in Ubuntu 14.04 LTS 64 bit.
library IEEE;
use…
Rezwan Khan
- 41
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2
votes
1 answer
PAD symbol "r<3>" has an undefined IOSTANDARD - Verilog
I was writing Booth Multiplier code in Verilog.
I'm getting the following errors.
PAD symbol "r<3>" has an undefined IOSTANDARD
PAD symbol "r<3>" is not constrained (LOC) to a specific location.
I Don't want to test it in FPGA. Just need to…
Jithin Pavithran
- 1,250
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2
votes
3 answers
Using BUFG to drive clock loads
I'm attempting to work with pixel data that is output to a DVI chip. A variety of clock frequencies are used because the DVI chip registers are programmed using I2C (therefore needs a clock < 500 KHz) - from a clock divider.
The DVI chip needs a 40…
davidhood2
- 1,367
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- 47
2
votes
1 answer
Width mismatch: Variable in vector range for signal assignment. why and how to fix?
ISE 14.7 at synthesis returns the following warning on the subsequent line which eventually leads to an error:
"Width mismatch. has a width of 8 bits but assigned expression is 128-bit wide."
temp <= padding_start_s((((i_pad+1)*8)-1) downto…
toxUP
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2
votes
1 answer
implementing a 50ns delay in VHDL
I'm sending data to and A/D converter and I need the command data to be delayed at least 50ns from clk_19khz. Here is what I have so far.
How do I insert a delay of 50ns which is a requirement for the A/D between the clk_19khz and my first Dout bit…
hfbroady
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2
votes
1 answer
How can I locate inferred latches in Xilinx ISE?
I have a big design in Xilinx ISE, there are 3 inferred latches which I would like to remove. Threre is no IP core or Microblaze and I have written all the code myself. I have problem locating the latches in my design. I have searched through report…
dopamine
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- 2
2
votes
2 answers
Using Custom Packages Causes Circular Dependency
I'm trying to declare an unsigned array in a package so that I can use the same type of array across all of my components. I declared it in the top-level component first, and then used the work library and use command to call on the package in each…
Eugene Wu
- 61
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2
votes
0 answers
Can't add source in Xilinx 14.2
I am currently using ISI Design Suite (Xilinx) 14.2 version in Windows 8.1. I want to Add Source from a location to my main file but whenever I click on Add Source option, the software Xilinx gets closed every time I do that.
Akash Soni
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