Highest Voted 'xilinx-ise' Questions

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Synthesis error of Array Multiplication with an input

Hello I am trying a small section of a project code where the equation is multiplying input with all values of array and then adding them up in one final output. module arraywithinput(input in, output reg [11:0] out0 ); reg [7:0]…

asked Oct 18 '21 at 07:10

Arslan Majid

39
8

-1

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1 answer

Program Spartan6 eFUSE key in w10

I need help programing efuse registers on Spartan 6 from windows 10. We have plethora of boards designed with the Spartan 6. We are currently programming them with an old Windows XP machine which needs to be retired and replaced with windows…

xilinx-ise jtag spartan

asked Jul 26 '21 at 12:34

Joshua

1,185
14
23

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1 answer

I'm getting an syntax error in my VHDL code near counter

I'm trying to simulate a pulse width modulate (PMW) waveform generator and getting a syntax error in ISE. Checked fuse.xmsgs and found out it's near counter. Can someone point out the syntax error, please? library IEEE; use…

syntax-error vhdl simulation pwm xilinx-ise

asked Jun 10 '21 at 12:57

Jason Jackobs

3
1

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1 answer

Xilinx ISE 14.5 doesn't ask for a .ucf file, and probably doesn't read it

Good day! I have a following issue: I am using Xilinx ISE 14.5 to design for a Spartan 6 FPGA. I noticed that is one of my designs I wasn't able to change the physical pin mapping for a signal. When I changed the line in the .ucf file to another…

vhdl fpga xilinx-ise

asked Sep 21 '20 at 14:28

Anthropomorphous Dodecahedron

119
1
5

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1 answer

Xilinx ISE: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"

I am writing Bin to BCD code Multiplier and in the top module Xilinx ISE gives this error: Line 30: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+" while I have mapped the ports to the top…

vhdl fpga xilinx xilinx-ise

asked Jul 01 '20 at 07:34

Banana Guy

1

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1 answer

How to connect 2 ports(input) to same wire in verilog

Instantiate the following module connecting ports by name. The output of the module should be connected to wire S, port B should connect to wire T, and port C should also connect to wire T. my_module(output A, input B, input C); How can I write…

verilog xilinx-ise system-verilog-dpi

asked Feb 27 '20 at 18:59

Hassaan

11
3

-1

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1 answer

verilog code is working in isim(xilinx 14.2) but is not working onspartan6

i have written a simple counter code in verilog (xilix 14.2). The code is working properly in the isim but i am not able to dump it onto spartan6. When I try to do dump the code, a red light is ON , on the spartan 6 and the code is not dumped .…

verilog fpga xilinx-ise spartan

asked Dec 07 '18 at 16:57

user10759984

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votes

1 answer

Transmitting data rate and Receive Window Size

Nowadays, I am making a project relating to protocol communication between 2 FPGA. When I read information about TCP/IP ethernet, the window receive which the amount data that computer can accept. And there are a relationship between Window receive…

networking xilinx xilinx-ise

asked May 27 '18 at 10:31

Tai Chau

33
1
9

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1 answer

Error while checking syntax

module mult(a, b, p); input [16:0] a; input [16:0] b; output p; wire [31:0] p; reg i; wire pv; wire bp; assign pv = 32'b0; assign bp = {16'b0,b} ; initial begin for (i = 0; i < 32 ; i = i + 1) begin …

verilog xilinx xilinx-ise

asked Feb 14 '17 at 06:09

prakash Sri

1
3

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1 answer

file does not exist in VHDL

I want to read from a text file and show it in the ISE environment, I have the code below, but when I run it the error: File does not exist. is created, I have the test.txt file in the folder that the codes sources exist in. What is…

vhdl xilinx xilinx-ise

asked May 02 '16 at 06:59

Sheyda Alizadeh

7
3

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2 answers

need your help for the following vhdl code in Xilinx tool

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity conv_enc is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; inp : in STD_LOGIC; outp : out …

vhdl xilinx xilinx-ise xilinx-edk

asked Apr 18 '16 at 11:35

haftish

9

-1

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2 answers

ISim Post-Route Simulation ERROR

I was attempting to test a VHDL project with Isim Simulator within ISE. Behavioral simulation works fine while Post-Route produces a lot of errors of this kind: Warning: /X_FF PULSE WIDTH High VIOLATION ON RST; Expected:= 1.794 ns; Observed:=1.369…

vhdl simulation fpga xilinx xilinx-ise

asked Feb 25 '16 at 17:09

Mazzola

75
7

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2 answers

Cycle delay in Verilog

I have been struck at this point for quite some time now and would really help me out if someone can look into this and solve it. There are 4 inputs to a system - w, a,b,c. All are periodic inputs which are changing with time. The output is o. All…

verilog xilinx-ise

asked Jan 28 '16 at 14:24

Shivang

1
2

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1 answer

Error on converting bit files to ace files

I want to convert .bit file to .ace file using the command prompt. I try to create .bat file to do that. But when I execute the command, no files are added to the specified directory. The batch file is named makeace and has this code: @echo off if…

batch-file xilinx xilinx-ise xilinx-edk

asked Oct 25 '15 at 18:05

sepeee

47
1
6

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1 answer

Square Waveform Generation

I'm working on a stopwatch project in VHDL, but I don't know how to make the CLK square waveform of the counter? Here is my code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; entity Circuit is Port ( CLK : in …

vhdl xilinx-ise

asked Apr 29 '15 at 13:32

user3417785

81
1
6

Questions tagged [xilinx-ise]