Xilinx ISE is the toolchain package for programming Xilinx FPGAs in VHDL and Verilog.
Questions tagged [xilinx-ise]
291 questions
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1 answer
Key expansion module of AES on Xilinx : error : multisouce on signal
This is code written in VHDL on Xilinx 9.2 ise. NK = 4 NR = 10; VALUE=43; K_IN is the key from the user in the form of
type STATEX is array(0 to 3, 0 to 3) of std_logic_vector (7 downto 0);
K_OUT is the output of
type KEYWORD is array (0 to 43) of…
Nilima Parmar
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1 answer
assign output array correctly
How do I assign a input-bus to an output-bus without having to assign every index (without loops).
I had something like that in mind:
module test(input [2:0] in, input CLK, output [2:0] out);
reg [2:0] state;
always @(posedge CLK) state <= in;…
k t
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how to instantiate a dsp slice in virtex 6?
i am working on a vhdl code (virtex 6). where i need to do number of multiply and accumulate operation. how do i use dsp slices for this(an in the instantiation and inference). Are there any examples which can help me?
rashmi mahesh
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1 answer
Suggesting Implementation of an Algorithm on FPGA
As a course project, I have to implement an algorithm on FPGA. Currently I'm considering arithmetic algorithms and ideas like implementation of 4 basic operators for floating point numbers come to mind. As I'm new to such topics I'd be thankful if…
Ahmad Siavosh
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2 answers
VHDL Coding: 10 bit Decimal conversion to BCD is it possible?
Good Day,
My latest assignment is to convert the 10 bit decimal (since the maximum decimal number of 10 bit is 1023) to 16 bit BCD. When the input decimal is greater than or equal to 1024, then the error waveform will go high. The whole module of…
c2s1
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3 answers
Cannot understand the errors in my code
I'm working on t-bird lights controller and I keep getting these errors in my code and when I go through the code there is nothing really wrong with it! I don't have much experience in VHDL but I can tell if it is right or wrong, please I need your…
Abbey Nour
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