Highest Voted 'xilinx-ise' Questions

2

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Error in generate programming file in xilinx EDK

while working on Xilinx EDK to implement a simple design using embedded softcore IP, we have hit a few hurdles, following is the detailed outline of the problems we are facing. as per our understanding, we followed the following steps involved for…

xilinx xilinx-edk xilinx-ise

asked Jul 28 '14 at 18:40

Himanshu Sourav

700
1
10
35

2

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1 answer

Is there any documentation for Xilinx (ISE) filter files?

I'm looking for a documentation on Xilinx ISE *.filter files. Here is a short example of a Message/Warning/Error filter entry: button_center In this…

vhdl verilog xilinx xilinx-ise

asked Jun 27 '14 at 06:09

Paebbels

15,573
13
70
139

2

votes

0 answers

While loop stops no error or warning message in Xilinx SDK on Zynq processor

I am using a sensor and reading values from it. I have added uart_lite in the xilinx EDK and mapped it's pins to the boards GPIO. The PS (Zynq PS) clock is 50Mhz/100Mhz/200Mhz. I am receiving data from the RX of UART at 115200 baud rate with 2 stop…

c sdk embedded fpga xilinx-ise

asked May 30 '14 at 07:35

user3442775

1

vote

0 answers

Russian peasant multiplication in VHDL

I'm using Xilinx ISE to compile and simulate VHDL code. And I'm trying to compute the multiplication of two 8-bit numbers using the Russian algorithm. The following code is how I'm currently doing it: library ieee; use ieee.std_logic_1164.all; use…

vhdl xilinx-ise

asked May 26 '23 at 00:05

Amirreza A.

736
4
10

1

vote

1 answer

How to add integer based vhdl inout signal to ucf file

I'm completely new to VHDL and I wrote a code that's supposed to be a 16*4 RAM memory.I wrote a VHDL and VHDL testbench for it and I tried to add a user constraints file(ucf) to it and everything seems fine,except that It gives error on four of my…

vhdl fpga xilinx xilinx-ise

asked May 29 '22 at 18:34

adabella asi

99
6

1

vote

1 answer

How to properly instantiate a module and pass registers to it

[![Simulation: modules seem to be running but not passing/recieving appropriate info?][1]][1] I'm trying to become familiar with the Xilinx iSim utility. I am comfortable simulating a single, self contained module. However, when I begin introducing…

verilog xilinx-ise

asked Jan 22 '22 at 18:35

Tesla047

43
7

1

vote

1 answer

What is the reason behind the warnings (Xst:3015) and how to rectify the same?

This is my warning message WARNING:Xst:3015 - Contents of array may be accessed with an index that does not cover the full array size or with a negative index. The RAM size is reduced to the index upper access or for only positive index…

verilog compiler-warnings xilinx hdl xilinx-ise

asked Dec 12 '21 at 12:17

vishnu lal

23
4

1

vote

1 answer

16 to 1 mux using 2 to 1 mux in vhdl

I'm trying to write a code in vhdl to create a 16 to 1 mux using 2 to 1 mux. I actually thought that to do this we may need 15 two to one multiplexers and by wiring them together and using structural model I wrote the code below. First I wrote a 2…

vhdl xilinx digital xilinx-ise

asked Jun 06 '21 at 13:46

maryam gh

163
1
5
11

1

vote

1 answer

4-bit comparator issue in vhdl

I am new to VHDL and I have an issue writing a 4-bit comparator. When I want to compare different sets of inputs there is only one output for all of them. And I don't know how to solve this problem. I want to have only one output and need to show…

vhdl hardware comparator xilinx xilinx-ise

asked Apr 28 '21 at 13:08

maryam ghanbari

25
6

1

vote

0 answers

7 4 Hamming decoder in xilinx (Shows warning "temp should be on the sensitivity list of process")

This is what I am implementing. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity sammy_2018314405 is Port ( codeword : in STD_LOGIC_VECTOR (6 downto 0); syndrome : out STD_LOGIC_VECTOR (2 downto 0); dataword : out …

vhdl xilinx-ise

asked Mar 24 '21 at 14:23

David98

31
3

1

vote

1 answer

How to install Xilinx ISE 14.7 for Ubuntu 19.10

I have to work with a Spartan 3E family FPGA, my problem is that latest versions of Xilinx ISE does not support this boards. I made a quick search on google and I found that the last versión that supports Spartan 3E is 14.7 so I tried to install…

xilinx-ise spartan ubuntu-19.10

asked Dec 19 '20 at 15:18

rafael ayllón

9
1
3

1

vote

0 answers

Why am I getting a High Z output for cathode in seven segment display controller instead of a numeric value?

I wrote a verilog code for a seven segment display controller as part of my assignment, but in the simulation, i get the following error: Can someone please resolve this issue? I have attached the following verilog modules: 1.Main controller…

verilog xilinx-ise

asked Dec 12 '20 at 19:56

Mohammed Sanwal

19
3

1

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0 answers

What is the (Asynchronous Control Signals Information) subsection in the Xilinx ISE synthesis timing report supposed to include?

I wrote a simple VHDL code for a DFF with an asynchronous reset input here: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity DFF is port (d: in STD_LOGIC; q: out STD_LOGIC; clk: in STD_LOGIC; reset: in …

vhdl synthesis xilinx-ise

asked Sep 18 '20 at 13:10

Tortellini Teusday

1,335
1
12
21

1

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What does the PINNAME to PINNAME data path in Xilinx ISE synthesis timing report mean?

I've written a simple DFF with the following VHDL code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity DFF is port (d: in STD_LOGIC; q: out STD_LOGIC; clk: in STD_LOGIC; reset: in STD_LOGIC); end…

synthesis xilinx-ise

asked Sep 18 '20 at 12:37

Tortellini Teusday

1,335
1
12
21

1

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1 answer

Programming multiple devices parallelly using Vivado

We have a setup where two Xilinx FPGA devices are individually connected to a computer. We use Vivado Tcl Console to program the FPGAs in our automation environment. I am able to successfully program the two devices one after the other. However, I…

tcl xilinx vivado xilinx-ise

asked Sep 18 '20 at 07:48

Kannan D

467
1
4
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Questions tagged [xilinx-ise]