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Questions tagged [xilinx-ise]

Xilinx ISE is the toolchain package for programming Xilinx FPGAs in VHDL and Verilog.

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Baysis2 Verilog - First Digit of 7 Segment Display Wont Work

I'm trying to create a simple 4 digit password system on my baysis2 FGPA using verilog. I want to use the 7 segment display to display the digits as they are entered (they will be entered using a keyboard). Right now I'm just testing to make sure…
Noah Mendoza
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Baysis2 Keyboard ports always high

I'm trying to create a password system with a baysis2 FPGA and verilog that verifies a password which is entered via keyboard. I need to make sure that my keyboard is working properly, as it seems to be a bit glitchy. I was told that the best way to…
Noah Mendoza
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Initializing ROM from array using functions, Synthesis ERROR (VHDL)

Ok, so I have a problem with a ROM initialization function. Before I get into the problem let me explain a bit the nature of my problem and my code. What I want to do is generate N number of ROMs which I have to use as an input for a module that…
Nailtha
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Why does incrementing a std_logic_vector give unknown value?

I'm attempting to write a I2C bus master in VHDL - and thoroughly test it to ensure it works etc. In doing so, I've written the module and a subsequent test-bench to test it under different stimuli - namely changing addresses and data input after…
davidhood2
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Maximum clock delay Xilinx ISE

My design uses an Xilinx FPGA. The synthesis report shows the following results: Timing Summary: --------------- Speed Grade: -3 Minimum period: No path found Minimum input arrival time before clock: 1.903ns Maximum output required time…
MrFPGA
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HDL Compiler Error 806 for Verilog HDL Test Fixture (Shift Register)

So I am doing a pre-lab assignment for my digital systems course in which we are supposed to test certain components and ultimately create a counter from them. The issue I'm having is that the code the professor gave us won't compile. This specific…
kgEE19
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Please Explain these verilog code?

code of booth multiplier is :- module ni(prod, a, b, busy, mc, mp, clk, start); output [15:0] prod; output [7:0] a, b; output busy; input [7:0] mc, mp; input clk, start; reg [7:0] A, Q, M; reg Q_1; reg [3:0] count; wire [7:0] sum, difference; always…
Mukesh Gupta
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Errors in VHDL Xilinx ISE Project Navigator

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DruigZadatak is Port ( iSW : in STD_LOGIC_VECTOR (7 downto 0); iSEL : in STD_LOGIC; oLED : out STD_LOGIC_VECTOR (7 downto 0)); end DruigZadatak; …
xena12
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Synchronously Counting Debounced Button Presses in VHDL

The following code is a VDHL module in Xilinx ISE 14.7 that counts debounced button presses (iXXX), tests to see if they have reached a max, and outputs a "value" for each accumulated input to a std_logic_vector (oXXX) that will be displayed on a…
Boone Angel
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Activating/Using ISim tool chain with Eclipse (VHDL)

I'm attempting to program very basic VHDL on eclipse using the Sigasi plugin with an educational license - with the aim to be, I can program a simple entity and a test bench for it, then compile and simulate it in Xilinx's ISim. I have installed…
davidhood2
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Implementation error in ISE for a Virtex-5 board

I'm using a Xilinx Virtex-5 version XC5VLX110T in ISE project navigator 14.6 to test a simple code but it always give implementation design error: ERROR:Security:12 - No 'xc5vlx110t' feature version 2013.06 was available (-15), ERROR:Map:258…
sepeee
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unsynthesizable VHDL code

I am trying to make a DNA reader module using VHDL processes for Spartan-S6 series FPGA. The problem is that my code couldn't be synthesized. It works on simulation but in synthesizing it just stucks. I also googled about unsynthesizable VHDL…
reza
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Four Bit Adder Understanding

Can someone explain to me what I am doing wrong. I don't know if I just don't understand the concept or what. I have looked at two solid examples, both of which provide thorough code but maybe I am wiring things wrong or something. 1st - I have…
Marcus Burkhart
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ISE iMPACT program failing using Spartan-3AN

I would like to program my Xilinx Spartan-3AN using ISE but for the last step (using ISE iMPACT), the program is failing. In fact I've put a ".bit" file into the first chip but I don't have any ".mcs" file to put into the second chip so I tried to…
Cabs
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adding a serial port vivado/ISE microzed board-Xilinx

I am running xillinux on my microzed board. I need to define a new serial port on the board using vivado. I was able to add this to the IP core and the device is ready. But,how do I make this port visible on ubuntu (xillinux) like ttyPS0. DO I need…
bobbydf
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