Baysis2 Verilog - First Digit of 7 Segment Display Wont Work

Question

I'm trying to create a simple 4 digit password system on my baysis2 FGPA using verilog. I want to use the 7 segment display to display the digits as they are entered (they will be entered using a keyboard). Right now I'm just testing to make sure that the right numbers show up when they are entered. The problem is, the first digit of the seven segment display doesn't light up when all of the other ones do. I've tried it on multiple board and all of the other digits, which are enabled by the same wire, are fine. Why is this happening?

module enter_password(
    input wire clk, reset,
    input wire ps2d, ps2c, rx_en,
    output wire [6:0]  seven_seg_display,
    output wire assert_seg);

    wire [7:0] scan_out;
    wire [7:0] ascii_code;

    //initial seven_seg_display = 7'b0000000;

    assign assert_seg = 1'b1;

    // instantiate ps2 receiver
    ps2_rx ps2_rx_unit(
      .clk(clk), .reset(reset), .rx_en(1'b1),
      .ps2d(ps2d), .ps2c(ps2c),
      .rx_done_tick(scan_done_tick), .dout(scan_out));

    // instantiate key-to-ascii code conversion circuit
    Scan_to_ascii key2ascii(.key_code(scan_out), .ascii_code(ascii_code));

    assign seven_seg_display =  
       ascii_code == 8'h30 ? 7'b0000001: //0
       ascii_code == 8'h31 ? 7'b1001111: //1
       ascii_code == 8'h32 ? 7'b0010010: //2
       ascii_code == 8'h33 ? 7'b0000110: //3
       ascii_code == 8'h34 ? 7'b1001100: //4
       ascii_code == 8'h35 ? 7'b0100100: //5
       ascii_code == 8'h36 ? 7'b0100000: //6
       ascii_code == 8'h37 ? 7'b0001111: //7
       ascii_code == 8'h38 ? 7'b0000000: //8
       ascii_code == 8'h39 ? 7'b0000100: //9
                             7'b1111111; //e for error 0
endmodule

ucf

NET "seven_seg_display[6]" LOC = "L14"; # Bank = 1, Signal name = CA
NET "seven_seg_display[5]" LOC = "H12"; # Bank = 1, Signal name = CB
NET "seven_seg_display[4]" LOC = "N14"; # Bank = 1, Signal name = CC
NET "seven_seg_display[3]" LOC = "N11"; # Bank = 2, Signal name = CD
NET "seven_seg_display[2]" LOC = "P12"; # Bank = 2, Signal name = CE
NET "seven_seg_display[1]" LOC = "L13"; # Bank = 1, Signal name = CF
NET "seven_seg_display[0]" LOC = "M12"; # Bank = 1, Signal name = CG
#NET "dp" LOC = "N13"; # Bank = 1, Signal name = DP

NET "assert_seg" LOC = "K14"; # Bank = 1, Signal name = AN3
NET "assert_seg" LOC = "M13"; # Bank = 1, Signal name = AN2
NET "assert_seg" LOC = "J12"; # Bank = 1, Signal name = AN1
NET "assert_seg" LOC = "F12"; # Bank = 1, Signal name = AN0

Why is `assert_seg` assigned to 4 pins? Thid code should not pass the 'translate' step. Your code has no time multiplexer for the 7-segment display it is needed to drive all 4 digits. See the schematic of the board for clarification. — Paebbels, Nov 26 '15 at 06:48
Have you tried asserting the lowest bit only? That is, `wire assert_seg[3:0]` - `assert_seg = 4'b0001` - `NET "assert_seg[0]" LOC = "K14"`. The circuit is designed to run only one of the 7-segment displays at any time(with an updating frequency which is higher than the human eye can perceive). Perhaps it can't properly show one value continously on all displays. [Source](http://www.digilentinc.com/Data/Products/BASYS2/Basys2_rm.pdf) — Hida, Nov 26 '15 at 08:56

e19293001 · Answer 1 · 2015-11-26T03:16:12.980

The problem is, the first digit of the seven segment display doesn't light up when all of the other ones do.

I assume that there are two digits in your seven segment display so you need to have an output of 14-bit seven_seg_display from your enter_password module

Change

    output wire [6:0]  seven_seg_display,

to

    output wire [13:0]  seven_seg_display,

You'll also might have to change the logic of the following code to support a 14-bit seven_seg_display and a multiplexer to determine which half of seven_seg_display will be ascii_code assigned:

    assign seven_seg_display =  
       ascii_code == 8'h30 ? 7'b0000001: //0
       ascii_code == 8'h31 ? 7'b1001111: //1
       ascii_code == 8'h32 ? 7'b0010010: //2
       ascii_code == 8'h33 ? 7'b0000110: //3
       ascii_code == 8'h34 ? 7'b1001100: //4
       ascii_code == 8'h35 ? 7'b0100100: //5
       ascii_code == 8'h36 ? 7'b0100000: //6
       ascii_code == 8'h37 ? 7'b0001111: //7
       ascii_code == 8'h38 ? 7'b0000000: //8
       ascii_code == 8'h39 ? 7'b0000100: //9
                             7'b1111111; //e for error 0

Baysis2 Verilog - First Digit of 7 Segment Display Wont Work

1 Answers1