Highest Voted 'xilinx-ise' Questions

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Using Emacs as external editor of Xilinx ISE, how to change the related buffer to current buffer when click a design file?

It has been like one year or so since I started to learn Emacs, and I do like its power and flexibility as a general text editor. When I had tried its Auctex mode for LaTeX/TeX, I knew I will never go back to read which TeX editor I should use. When…

emacs xilinx-ise

asked Sep 13 '15 at 02:35

Fanpeng

332
1
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1 answer

How can I fix the warning " HDLCompiler: 1007 - Element index 7 into memp is out of bounds" when I describe the hardware RAM, using Verilog in Xilinx?

I have the following hardware description of a dual port RAM memory : module MemoryRAM #(parameter RAM_ADDR_BITS = 4, RAM_WIDTH = 8) (CLK, RAMEnableLSB, RAMEnableMSB, WriteMemory,LoadData, Address, OutputRAMMEM); input RAMEnableLSB, RAMEnableMSB…

verilog xilinx hdl xilinx-ise

asked Sep 12 '15 at 07:34

Adrian

171
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2 answers

Converting a std_logic_vector to integer within Process to test values?

What I'm trying to do is pretty simple, just generating a pulse from a basic counter. My code is shown below. My question is if there's an efficient way of comparing a std_logic_vector and an integer? I only need to compare them at that one…

vhdl xilinx xilinx-ise

asked Aug 20 '15 at 19:13

VKkaps

159
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2 answers

New DCM CLK instantiation error?

here's the code within the .xco file which was branched off my main vhdl file: -- The following code must appear in the VHDL architecture header: ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG component DCM_18 port (-- Clock…

vhdl xilinx xilinx-ise

asked Aug 18 '15 at 20:22

VKkaps

159
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1 answer

Reporting std_logic_vector as an unsigned integer in ISim?

here's the libararies I'm using: library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; the signal: signal CountTemp : std_logic_vector(15 downto 0); and the report statement: report "Actual…

vhdl xilinx xilinx-ise

asked Aug 06 '15 at 13:45

VKkaps

159
3
21

0

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1 answer

Issue formatting "if" statement within testbench process?

This has been driving me crazy. Here’s the code I have so far: signal SYS_CLK : std_logic := '0'; --Input signal InputSignal : std_logic := '0'; --Input signal SyncOutputSignal : std_logic; …

vhdl xilinx xilinx-ise

asked Jul 31 '15 at 16:28

VKkaps

159
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1 answer

Error while testing Assert statement in Xilinx

I'm currently recieving this error ERROR:HDLCompiler:1731 - Line ...: found '0' definitions of operator "=", cannot determine exact overloaded matching definition for "=" for my last 2 Assert statements shown below (PulseOutput and…

vhdl xilinx xilinx-ise

asked Jul 28 '15 at 18:09

user5153260

23
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3 answers

How to display the amount of errors that occured in a self-verifying testbench?

Below is my testbench code for a simple (unclocked) 4 bit Adder. My simulation currently will display any errors that occur along with a "Test Completed" at the end. If there are no errors, the simulation will simply return "Test Completed". My…

vhdl xilinx xilinx-ise

asked Jul 27 '15 at 14:43

VKkaps

159
3
21

0

votes

2 answers

VHDL: Default values in a Finite State Machine

I am trying to make a finite state machine that switches states based on serial input. I need some explanation regarding how my code is executed. I read in a textbook that the section in the process that I have marked "DEFAULT VALUES" is where I…

vhdl xilinx-ise

asked Jul 21 '15 at 17:02

Eugene Wu

61
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1 answer

generate statement with dsp48

I am new to VHDL and trying to create a project where i need to use dsp block for faster calculations on big numbers (256 bits). I created this DSP48macro using coreGenerator, however I am getting a syntax error for the generate statement. Please if…

vhdl fpga hdl xilinx-ise

asked Jul 21 '15 at 09:17

rdr1234

27
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1 answer

XILINX ISE set I/O Marker as Clock

I'm on Xilinx ISE IDE and using the Schematic Editor. (click for new window) The constraints file is following: NET "A" LOC = M18; NET "F" LOC = P15; NET "B" LOC = M16; NET "A" PULLUP; NET "B" PULLUP; NET "F" DRIVE = 8; But when I want to…

logic fpga xilinx xilinx-ise spartan

asked Jul 19 '15 at 12:43

Martin Fischer

697
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1 answer

VHDL Pulse Generator Seems Stuck

I am trying to build a pulse generator that consists of two pulse generators driven by a mod-m counter. The counter loops through a cycle with a set time, and whenever it hits some specified times, the pulse generators will generate short, square…

vhdl fpga xilinx-ise

asked Jul 08 '15 at 16:57

Eugene Wu

61
8

0

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1 answer

How can I merge several Xilinx NGC netlists to an new netlist

I'm using XST (synthesis tool in the Xilinx ISE 14.7 suite) to compile VHDL source files to a netlist (*.ngc file). My code uses several Xilinx IP Cores like ChipScope ILAs for debugging, which are also pre-synthesized as ngc files. I would like to…

vhdl xilinx synthesis xilinx-ise netlist

asked Jun 11 '15 at 12:00

Paebbels

15,573
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1 answer

Error in blackbox xilinx system generator

I use Xilinx system generator blocks in Matlab and i find the block black box wich can generate and simulate vhdl code. I programme a simple program in vhdl for port and, --import std_logic from the IEEE library library ieee; use…

matlab vhdl xilinx-ise black-box

asked May 11 '15 at 18:04

Marie

1
3

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0 answers

Why is my Xilinx ISE Simulator crashing?

I am trying to make an ALU for floating point numbers.This is my code and whenever I try to run simulation of a testbench waveform simulator crashes stating this: isim_beh.exe has stopped working library IEEE; use IEEE.STD_LOGIC_1164.ALL; use…

vhdl xilinx-ise

asked May 08 '15 at 11:13

Arslan

35
7

Questions tagged [xilinx-ise]