Highest Voted 'xilinx-ise' Questions

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Matlab System generator: error with black box

I using Xilinx system generator blocks in Matlab. I simply using only a black box with a gateway in and gateway out. The code for the black box is very simple and work correctly with ISE design suite library IEEE; use IEEE.STD_LOGIC_1164.ALL; use…

asked May 14 '16 at 02:13

Serwan Bamerni

78
1
9

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Increase the signal's time axis length in xilinx ise simulator

I am working on a project(VHDL). I have generated a test bench of the top module having clk and reset signals. When I don't use reset in the process in the test bench my simulator shows the clock signals all the way up to 1000 ns (desired here) but…

vhdl xilinx xilinx-ise

asked May 10 '16 at 19:21

Sunil Kumar

390
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7
25

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An error in VHDL code in Xilinx ISE

I am trying to write a 1-bit comparator VHDL code in Xilinx ISE. There are no errors in the code but when I tried to create a schematic symbol, this error has arisen: ERROR: G:/eq/eq.sym was not updated. Set the 'Overwrite Existing Symbol' process…

vhdl xilinx-ise

asked Apr 24 '16 at 17:17

maryam

23
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Constructing a 20kbit bit_vector data from 16bit unsigned_vector

I'm very new in VHDL and having a problem about assigning values I guess. Let's say that I've a module that get an 16 bit input signal noisein_mono for every positive edge of the clock source. What I want is to construct a 20 Kbit long bit vector…

vhdl simulation xilinx-ise

asked Apr 12 '16 at 19:14

unnamed

840
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26
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1 answer

ModelSim SE 5.7: unexpected 'Z' and 'X'

While getting my feet wet with an old Spartan2-Board I tried to setup a 1-bit full adder with the Verilog code and accompanying testbench as below: module full_adder(s, cout, a, b, cin); output s, cout; input a, b, cin; wire t1, t2, t3; xor (t1,…

verilog xilinx-ise

asked Apr 11 '16 at 08:09

user2286339

184
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Verilog: Altenative way for indexing signal on the LHS

I'm using Xilinx that uses XST to synthesize my design. I ran into trouble when I write something like someReg[offest*index+:constant] <= someOtherReg;. The error given is 'Variable index is not supported in signal.' What I've gathered after…

indexing verilog xilinx hdl xilinx-ise

asked Mar 09 '16 at 22:53

user3697625

167
4
17

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1 answer

Errors about using buffer in VHDL project

I am a beginner to VHDL. I am trying to implement a simple project but I got some errors. The first one is about using buffers. This is my entity code: entity Demultiplexer is Port ( A : in STD_LOGIC; S : in STD_LOGIC_VECTOR (2 downto 0); …

vhdl xilinx-ise

asked Mar 09 '16 at 17:14

Mahmoud Anwer

164
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2
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Xilinx Number of LUT Slices decrease on pipelining

I am using Xilinx, particularly the family Spartan6. I am trying pipelining. I have successfully impleted a 3-stage pipeline and a 4-stage pipeline. There is a trend that i noticed, that is the number of LUT slices decreased, the number of register…

pipeline xilinx xilinx-ise spartan

asked Mar 08 '16 at 22:50

aakashgupta.0205

647
1
8
23

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1 answer

max_fanout property of Virtex-6 circuit is not applied

I have a 8192 row (13 bit address) and 12 bit width block ram. In Virtex-6, we have 36kb Block Rams. So ISE Design Suite implements my ram as three 36kb BRAM with 4 bit width. For timing issues, I want ISE to use individual flip-flops for each…

performance optimization verilog xilinx-ise

asked Mar 07 '16 at 07:13

Mohammad

69
10

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1 answer

Tip for 4-bit 2's complement subtraction

I have to design and implement a 4-bit processor for a course in uni using Xilinx, Virtex 6, VHDL. I don't really know what those all mean i'm only a first year student. These were the instructions we received for the program. We need to be able to…

binary twos-complement xilinx-ise

asked Dec 30 '15 at 15:33

user5103669

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1 answer

Why wont Xilinx ISE accept this statement in a state machine?

So i am currently doing a little project involving a hd44780 display. But since i want to write my own init sequence i decided to use a state machine. I am quite new to FPGAs an their programming coming from a Java background. This is my State…

verilog fpga xilinx-ise

asked Dec 22 '15 at 21:09

I4k

5
2

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1 answer

VHDL : Selector (Constant ' ' of type STRING) is an unconstrained array

I downloaded a VHDL LCD Library from http://www.intesc.mx/soporte and I'm getting the following error when checking Syntax : Started : "Check Syntax for LIB_LCD_INTESC_REVB". Running xst... Command Line: xst -intstyle ise -ifn {D:/My pc/My…

vhdl xilinx-ise spartan

asked Dec 08 '15 at 18:32

Roberto Cortez

3
4

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2 answers

Gated Clock in Clock Divider for a Square Wave

I recently have been designing a clock divider for my system - which I redesigned, and now has an asynchronous reset, which generates a synchronous reset for the rest of the system. To do this, I followed the answers & advice to my own question and…

time vhdl clock fpga xilinx-ise

asked Dec 04 '15 at 12:46

davidhood2

1,367
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How to execute task concurrently with other statements in an always block?

I am writing code for 8*4 RAM in Verilog. For each binary cell of memory, I am using an SR flip-flop. Initially, each cell is assigned 1'bx. The logic seems to be correct, but the output isn't. It is probably because statements are not getting…

verilog xilinx-ise

asked Dec 03 '15 at 13:26

user2585933

57
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7

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votes

1 answer

Synthesised Synthesis/Implementation

I'm attempting to create an I2C Bus, however I've stumbled into a very awkward problem - during the mapping part of implementation I get the warning that MapLib:701 - Signal SDA connected to top level port SDA has been removed. After digging back…

vhdl state-machine xilinx synthesis xilinx-ise

asked Dec 02 '15 at 15:41

davidhood2

1,367
17
47

Questions tagged [xilinx-ise]