Errors in VHDL Xilinx ISE Project Navigator

Question

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DruigZadatak is
 Port ( iSW : in  STD_LOGIC_VECTOR (7 downto 0);
       iSEL : in  STD_LOGIC;
       oLED : out  STD_LOGIC_VECTOR (7 downto 0));
 end DruigZadatak;

 architecture Behavioral of DruigZadatak is

begin
    oLED <= "11111111" when iSEL ='0' else
            oLED(3 downto 0) <= (iSW(5 downto 3) + iSW(2 downto 0)),
            oLED(6 downto 4) <= "111" when iSW(7)='1' else
            "110" when iSW(6)='1' else
            "101" when iSW(5)='1' else
            "100" when iSW(4)='1' else
            "011" when iSW(3)='1' else
            "010" when iSW(2)='1' else
            "001" when iSW(1)='1' else  
            "000" when iSW(0)='1';  
    oLed(7) <= '0' when iSW ="00000000" else
        iSEL;
 end Behavioral;

and i get following errors

ERROR:HDLCompiler:288 -Line 45: Cannot read from 'out' object oled ; use 'buffer' or 'inout'
ERROR:HDLCompiler:1731 -Line 45: found '0' definitions of operator "<=", cannot determine exact overloaded matching  definition for "<="
ERROR:HDLCompiler:288 -Line 47: Cannot read from 'out' object oled ; use 'buffer' or 'inout'
ERROR:HDLCompiler:1731 -Line 47: found '0'   definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR:HDLCompiler:854 -Line 39: Unit <behavioral> ignored due to previous errors.

if someone could explain to me what should i do that and why these errors keep coming out it would be great, thanks. i hope you understand what was the point of my project..

score 1 · Answer 1 · 2015-10-31T18:15:58.720

Your conditional signal assignment statement can't have another conditional signal assignment statement embedded in it.

Break the assignments into three pieces instead of two:

 architecture foo of DruigZadatak is

 begin
     oLED (6 downto 4) <= "111" when iSEL = '0' or iSW(7) = '1' else 
                          "110" when iSW(6)='1' else
                          "101" when iSW(5)='1' else
                          "100" when iSW(4)='1' else
                          "011" when iSW(3)='1' else
                          "010" when iSW(2)='1' else
                          "001" when iSW(1)='1' else  
                          "000" when iSW(0)='1';                       

     oLED ( 3 downto 0) <= "1111"                    when iSEL = '0' else
                           '0' & (iSW(5 downto 3) + iSW(2 downto 0)) ;
     oLed(7) <= '0'   when iSW ="00000000" else    
                iSEL;                      
 end architecture;

Also note the concatenation of the '0' to the result of the addition to make the right hand side expression length match the left hand side of the assignment.

These three assignments are elaborated into equivalent processes with if statements. You could combine the if statements into a single process, they all would have identical sensitivity lists.

With VHDL -2008 compliant tools you could use sequential conditional signal assignment statements in a single process.

The above architecture with three concurrent signal assignment statements analyzes, elaborates and simulates (telling us there are no length mismatches and everything connects up).

This is my first project in xilinx vhdl, so everything is new to me, so can you explain me the last part with " '0' & ...." what's & for? and how is at the end iSEL=1? And will this work with architecture behavioral? — xena12, Oct 31 '15 at 18:49
Xilinx isn't synonymous with VHDL. "&" is a concatenation operator in this case creating a std_logic_vector with a length 1 greater than the "+" result by prepending a '0' to the result. 'how is at the end iSEL=1?' doesn't parse well in English (synthesis only deals with binary equivalent values, if it's not a '0' it's a '1'). You can name an architecture anything you want. VHDL supports multiple architectures. Your Xilinx tools likely allow you to specify the architecture you use, or otherwise the default binding indication would indicate the last one analyzed. — , Oct 31 '15 at 19:45

Errors in VHDL Xilinx ISE Project Navigator

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