Four Bit Adder Understanding

Question

Can someone explain to me what I am doing wrong. I don't know if I just don't understand the concept or what. I have looked at two solid examples, both of which provide thorough code but maybe I am wiring things wrong or something.

1st - I have created an file called Adder and below is my code. This works completely fine, I have created/ran a test bench file with this so I know this does exactly what is intended. However, am I supposed to somehow connect my FullAdder file or the test bench for the FullAdder file to the Adder file? Are these completely separate files and are never connected?

module Adder (a,b,ci,co,s);
    input a,b,ci;
    output co,s;
    assign s=a^b^ci;
    assign co=(a&b)|(a&ci)|(b&ci);
endmodule

2nd - Below is my code for the FullAdder file. I am not sure if this is correct but let me know where I can make possible changes. I assume the test bench I create will be linked to this FullAdder file? The syntax for this file checks out alright, so maybe it is the test bench that is causing problems for me...

module FullAdder(a,b,ci,s);
    input [3:0] a,b;
    input ci;
    output [3:0] s;
    wire [2:0] co;  // Is the wire correct here? I created this off something I saw.

    Adder ADD1(a[0],b[0],ci,s[0],co[0]);
    Adder ADD2(a[1],b[1],co[0],s[1],co[1]);
    Adder ADD3(a[2],b[2],co[1],s[2],co[2]);
    Adder ADD4(a[3],b[3],co[2],s[3],s[4]);
endmodule

3rd - I don't understand the test bench and wiring everything all together. I have looked at these two links which have two different ways of doing this. Link 1 Link 2. I have tried to replicate link 2, but can't seem to get it working. Help?

`s[4]` is out of range. Either expand `s` or manage the last carry out in a different way. — Greg, Oct 16 '15 at 22:03
Ok, I see that. Instead of s[4] do would think I should do something like co[2] at the end again? — Marcus Burkhart, Oct 16 '15 at 22:09

score 0 · Answer 1 · answered Oct 16 '15 at 22:18

Adder ADD4(a[3],b[3],carry[2],s[3],s[4]);

This instantiation assumes that s is a vector with an element in position 4, but your definition of s is [3:0] so 4 is not a valid position. Change it to

output [4:0] s;

It's desiderabel to use the Verilog 2001 module definition style (resembles ANSI C). Your module would be like this:

module FullAdder (
    input wire [3:0] a,
    input wire [3:0] b,
    input wire ci,
    output wire [4:0] s
    );

    wire [2:0] co;

    Adder ADD1(a[0],b[0],ci,s[0],co[0]);
    Adder ADD2(a[1],b[1],co[0],s[1],co[1]);
    Adder ADD3(a[2],b[2],co[1],s[2],co[2]);
    Adder ADD4(a[3],b[3],co[2],s[3],s[4]);
endmodule

Regarding your test bench (link 2) you mispelled some names: the name of 1-bit address is called "adder", not "Adder". Change either the definition or the instance name. The name of the ports are a,b,cin and s, not p,q,ci and r. These last are the signals (wires) you will connect to your ports.

As this adder has a limited set of inputs, I'd suggest to do an exhaustive test bench. So instead of probing two sample values for a,b and cin, try all the posibilities, and check that the result is the expected one. Something like this:

// Code your testbench here
module test_bench;

    // Inputs
    reg [3:0] p;
    reg [3:0] q;
    reg ci;

    // Outputs
    wire [4:0] r;

    // Instantiate the Unit Under Test (UUT)
    FullAdder uut (
        .a(p), 
        .b(q), 
        .ci(ci), 
        .s(r)
    );

    initial begin
      ci = 1'b0;
      repeat (2) begin
        p = 4'b0000;
        repeat (16) begin
          q = 4'b0000;
          repeat (16) begin
            #10;
            $display ("%b + %b + %b = %b", p, q, ci, r);             
            if (r != (p+q+ci)) begin
              $display ("ERROR!. Expected %b", p+q+ci);
              $finish;
            end
            #10;
            q = q + 1;
          end
          #10;
          p = p + 1;
        end
        #10;
        ci = !ci;
      end
      $display ("EVERYTHING OK!");
      $finish;
    end
endmodule

See http://www.edaplayground.com/x/HR5

Ok I will try this. First off, the "Link2" was just one I found, that was not my code. I was trying to replicate it. Secondly, The link you provided, Module Adder and Module FullAdder are two separate files correct? They are not combined into one big file as shown in the link? So essentially you have 3 files, one called Adder, one called FullAdder, and one called TestBench? — Marcus Burkhart, Oct 16 '15 at 22:24
I have three modules. Two of them are in one file, and the test bench is in a separate file. You can put the three modules in the same file if you want, or one file per module — mcleod_ideafix, Oct 16 '15 at 22:59

Four Bit Adder Understanding

1 Answers1