Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language (hdl) and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - fpga), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - asic) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of verilog, IEEE 1364-2005.

3298 questions

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1 answer

How do i translate PSL or SVA liveness assertions / properties into Verilog?

how can I translate PSL or SVA liveness assertions into verilog either by hand or automatically using a (open source) tool? i can do simple safety properties but i have no clue about liveness properties. i know some commercial tools have this…

verilog system-verilog formal-verification model-checking system-verilog-assertions

asked Feb 17 '15 at 08:26

adrianX

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1 answer

How do I concatenate parameters and integers?

My code for an Altera FPGA has 8 memories, that I need to initialise using memory initialization files (mifs). To enable me to instantiate memories with different mifs, I make the following changes to the memory definition file. original code module…

verilog system-verilog quartus intel-fpga

asked Feb 10 '15 at 23:31

Prashant

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1 answer

file/Multi-channel descriptor (2) passed to $fclose is not valid

This is a follow up question to one posted on Feb. 5. I did not know how to follow-up that thread, hence this new question. I have updated test bench attached. It contains $fwrite etc. as suggested. Now getting warning: file/Multi-channel…

verilog system-verilog fclose

asked Feb 08 '15 at 15:12

Bhal Tulpule

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2 answers

Assertion to verify a glitch in a signal

Lets say there is a signal a . When the signal goes high, it has to stay high at least for three positive clock edges. We can write the property as property p; @(posedge clk) $rose(a) -> a[*3]; endproperty The property fails for the case below. clk…

system-verilog assertions system-verilog-assertions

asked Feb 08 '15 at 04:39

user1978273

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1 answer

Does $stable in SystemVerilog Operate on Buses?

I would like to verify that a bus is stable in an assertion. For example, I would expect the following assertion to flag an error if data changes in the clock after the re falling edge. wire clk, rst_n, re; wire [15:0] data; a_chk_stable_data: …

system-verilog assertions system-verilog-assertions

asked Feb 02 '15 at 16:06

Cody

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1 answer

UVM Register Model: volatile register value change

Is there a standard way to wait any value change in volatile register model? This would be like doing backdoor access peek() periodically through all volatile register until there is at least one value change. // wait until DUT modifies any volatile…

system-verilog uvm

asked Jan 30 '15 at 03:53

AldoT

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1 answer

Why systemverilog 4 state variables require more memory?

It is given in the systemverilog LRM that 4 state variables require more bits to encode X and Z . How are these X and Z encoded ?

types verilog system-verilog

asked Jan 25 '15 at 22:59

Amardeep reddy

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1 answer

Inferring latches in Verilog/SystemVerilog

The statements in procedural blocks execute seqeuntially so why aren't any of the block1, block2 or block3 inferring a latch? module testing( input logic a, b, c, output logic x, y, z, v ); logic tmp_ref, tmp1, tmp2, tmp3; …

memory verilog system-verilog quartus

asked Jan 24 '15 at 22:40

evilpascal

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0 answers

is it possible to pass "event" as argument to module?

module top(); event e1; evnt i_evnt(e1); endmodule module evnt(input event e1); /* Program body */ endmodule when this modules complied it give error A Verilog keyword was found where an identifier was expected. How to pass event…

system-verilog

asked Jan 23 '15 at 09:13

Akshay Patil

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1 answer

How to check class randomized object result with its derived class constraint

Let say I have these two classes: class random_packet extends uvm_sequence_item; rand int cmd; ... endclass and its extension: class good_packet extends random_packet; constraint good_constr { cmd inside {0,1,2}; } …

system-verilog uvm

asked Jan 21 '15 at 07:55

AldoT

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1 answer

8 bit wide, 2-to-1 multiplexer verilog module

I'm having a lot of trouble making any sort of sense of this problem. I'm supposed to create a module for an 8 bit wide 2-to-1 multiplexer using Verilog. The question: Write a verilog module that uses 8 assignment statements to describe the…

verilog system-verilog

asked Jan 21 '15 at 00:10

user125535

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1 answer

NBA for dynamic objects

I have read somewhere that Non-Blocking-Assignment is not allowed for dynamic objects like class-objects, dynamic arrays etc. My sample code is class dyn_class; logic a; function void put(); a <= 1'b1; endfunction endclass module TB(); …

system-verilog

asked Jan 05 '15 at 19:45

user1978273

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1 answer

How to initialize clocking block signals at reset

I've been reading through UVM: illegal combination of driver and procedural assignment warning and paper attached in answer. (Please consider paper linked in the question mentioned) However drivers are implemented to drive reset values on interface…

system-verilog uvm

asked Jan 03 '15 at 19:48

wisemonkey

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2 answers

About struct in system-verilog?

I got vcs compile error when adding function in declaration of struct. The IEEE doc does not mention if function in struct is allowed. I also got vcs compile error when trying to assign a default value to a field. But it is allowed in IEEE-1800-2012…

system-verilog

asked Dec 19 '14 at 07:45

awill

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2 answers

wait($time >1000); cannot work in system-verilog?

I use this code to wait for a specific simulation time initial begin $display("A"); wait($time>1000); $display("B"); end the simulation result is: A I didnot see B printed. If I use following code, it works. while($time <1000) #1; Is…

system-verilog

asked Dec 17 '14 at 07:54

awill

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