Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language (hdl) and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - fpga), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - asic) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of verilog, IEEE 1364-2005.

3298 questions

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SystemVerilog data type map to VHDL

my problem is that I have an int_array generic in a VHDL entity and I want to set it from my SV tb. Which is the correct SV data type to do it? I tried several possibilities but no one of them was correct. Thanks in advance.

vhdl system-verilog

asked Dec 02 '14 at 16:15

arandomuser

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1 answer

What's the difference between queue.size() and queue.size

It seems queue.size() can also be written as queue.size and it also works. Is there any difference? Does that mean that all functions and tasks can be used w/o parenthesis?

system-verilog

asked Nov 28 '14 at 08:12

awill

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1 answer

Ring Oscillator code always shows Z for the output

I want to write code in Verilog for a Ring Oscillator. Here is my code: module RingOsci(enable, w1, w2, w3); input enable; output w1, w2, w3; wire w4; and (w4, enable, w3); not #2(w2, w1); not #2(w3, w2); not #2(w1,…

verilog system-verilog test-bench

asked Nov 22 '14 at 18:25

user3540595

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1 answer

SystemVerilog DPI-C pointers

I have a question about the DPI connection between SystemVerilog and C. Specifically, I have a C function that looks like: unsigned short C_FUN(unsigned char* data) and what I want to pass to it is a bit[7:0] my_darray[]; Which is the best way to…

c system-verilog system-verilog-dpi

asked Nov 22 '14 at 13:46

arandomuser

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FSM: next state precedence

When being in a state "a1" how can I show that the next arrows will have a precedence over each other, without having an overhead of extra states? Full example: We are at a1 state and signals x && y are asserted: we go to state b1 If that…

verilog system-verilog fsm state-machine operator-precedence

asked Nov 20 '14 at 14:34

user2692669

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6-bit binary counter with LED output shows X

I can't understand why my program returns nothing. I'm trying to make a simple 6-bit up-counter that counts on a button press. module top (CLK, BTN_RST, LED, BTN_C); input CLK, BTN_RST, BTN_C; output [5:0]LED; reg [5:0]LED; always…

verilog system-verilog test-bench

asked Nov 07 '14 at 13:10

bigbobr

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2 answers

Generate Conditional Assignment Statements in Verilog

I'm trying to create a simple crossbar style interconnect between N masters and M slaves. Say if I have 2 Masters and 2 Slaves, the crossbar connects them as follows: // Master - to - Slave assign s[0].addr = (gnt[0] == 1) ? m[0].addr : ( (gnt[1]…

verilog system-verilog

asked Nov 07 '14 at 10:31

sundar

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Calculating a parameter in a loop generate block

I have an array of parameters WIDTHS, and I need to calculate another parameter RIGHT based on some values in WIDTHS in a generate block. Is this possible? If not, is there an alternative way? Here is an example of what I am trying to do. Suppose we…

verilog system-verilog

asked Nov 06 '14 at 19:30

Ari

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Global randomization in systemverilog across tests

I have following class. Class A; randc int B; endclass In my test case I call randomization of this class only once. Will it make sure that value that I get across tests are unique? Randc will work only within a testcase mostly. Do we have…

system-verilog

asked Nov 04 '14 at 10:04

user2268152

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1 answer

Regd: Log assertion markers

How to make inverted triangle markers visible in Questsim environment. I am using wild card operator for logging waveform (.wlf). The markers are used for debugging assertion based verification.

verilog system-verilog modelsim

asked Oct 15 '14 at 21:05

user3593864

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1 answer

Groups inside structs

Can I have groups inside a struct? pseudo-code: typedef struct { input_group { logic a; } output_group { logic b; } } my_signals_list

data-structures system-verilog

asked Oct 09 '14 at 10:13

user2692669

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2 answers

How to test the current instance name?

I need to use the current instance name (full hierarchical name) in a generate if condition: generate if (current_instance_name() == "a.b.c.foo") ... Is there any way to do that in Verilog or SystemVerilog? I know %m, but it only allows to…

instance verilog system-verilog

asked Sep 30 '14 at 08:24

Laurent A

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3 answers

how to get rid of tr_db.log in uvm-1.2?

By default, UVM-1.2 generates a file "tr_db.log". It is quite inconvenient to run long simulations while generating this file. How can I disable it?

system-verilog uvm

asked Sep 25 '14 at 08:12

e19293001

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Concatenation operator in System verilog in a loop

I am trying to do the following : concat = {concat[7:0],clk} inside a forever loop as below : bit [7:0] concat; concat = 0; forever begin @(posedge clk); concat = {concat[7:0],clk}; end I wanted to know what value…

loops for-loop concatenation system-verilog

asked Sep 24 '14 at 11:35

user3714538

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2 answers

What is need of Assign/Deassign in Verilog?

I am here giving here 2 Verilog modules, which during simulation behaves same. But I don't understand that why to use assign/deassign in these modules, i.e. what is the difference between these 2 codes? // Code 1 - Without assign-deassign module dff…

verilog system-verilog

asked Sep 20 '14 at 05:57

Karan Shah

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