Why systemverilog 4 state variables require more memory?

Question

It is given in the systemverilog LRM that 4 state variables require more bits to encode X and Z . How are these X and Z encoded ?

Answer 1

For a simulator to keep track of a bit that has 4-states it requires 2 bits of real memory. The simulator might encode to some thing like:

2'b00:  zero
2'b01:  x
2'b10:  z
2'b11:  one

If using a 2-state it only requires 1 bit of memory to track it.

ie a 32 bit bus with 4 states would take 64 bits of memory for the simulator, but only 32 bits if using 2-state types.