This is a follow up question to one posted on Feb. 5. I did not know how to follow-up that thread, hence this new question.
I have updated test bench attached. It contains $fwrite etc. as suggested. Now getting warning:
file/Multi-channel descriptor (2) passed to $fclose in not valid
The AA2.txt file is empty. Used $fwrite (instead of $fmonitor) and it works but with same warning. Should I just ignore the warning ? I also tried to use "reset" (SEE CODE) based on the status of a DUT output signal (negedge ASM_FLAG) which goes from 1 to 0 at the end of simulation, to stop writing to file, but reset is always 1 so no output. It seems like the simulation has not started. Can you explain?
`timescale 1ns / 1ps
// Create Date: 16:57:34 12/04/2014
// Design Name: ADC_SAMPLE
// Module Name: C:/Xilinx131/SOC/SOC501V2/ADC_SAMPLE_tb.v
// Project Name: SOC501V2
//
// Verilog Test Fixture created by ISE for module: ADC_SAMPLE for review with Honeywell
//
// Revision 0.01 - File Created
module ADC_SAMPLE_tb;
// Inputs
reg CLK;
reg ASM_SEL;
reg [11:0] ADC_BUS;
reg [7:0] ADC_Wait_Time;
// Outputs
wire [7:0] ASM_HB;
wire [7:0] ASM_LB;
wire AS_SConv;
wire AS_OE;
wire ASM_FLAG;
wire [3:0] S;
parameter PERIOD = 100;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
// Instantiate the Unit Under Test (UUT)
ADC_SAMPLE uut (
.CLK(CLK),
.ASM_SEL(ASM_SEL),
.ADC_BUS(ADC_BUS),
.ADC_Wait_Time(ADC_Wait_Time),
.ASM_HB(ASM_HB),
.ASM_LB(ASM_LB),
.AS_SConv(AS_SConv),
.AS_OE(AS_OE),
.ASM_FLAG(ASM_FLAG),
.S(S)
);
initial begin
// Initialize Inputs
CLK = 0;
ASM_SEL = 1;
ADC_BUS = 12'hABC;
ADC_Wait_Time = 4;
end
initial
begin
#OFFSET;
forever
begin
CLK = 1'b1;
#(PERIOD-(PERIOD*DUTY_CYCLE)) CLK = 1'b0;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin
// Wait 100 ns for global reset to finish
// Add stimulus here
#200 ASM_SEL=1;
#150 ASM_SEL=0;
end
integer h1;
reg reset;
initial begin
reset = 0;
@(negedge ASM_FLAG) reset = 1;//at completion of sim, ASM_FLAG goes 0;
end
initial begin
$display("ADC_SAMPLE_tb simulator output");
$display ("h1,CLK, ASM_SEL,ASM_HB,ASM_LB,AS_SConv, AS_OE, ASM_FLAG,S");
end
initial begin
h1 = $fopen("AA2.txt");//did not work as a seperate init/begin block..
end
always @ (posedge CLK)
begin
repeat (10)
// while (reset == 0)
begin
$fwrite(h1,"%d,%b,%b,%b,%h,%h,%b,%b,%b,%h,\n",
h1,reset,CLK, ASM_SEL,/* ADC_BUS,ADC_Wait_Time,*/ASM_HB,ASM_LB,
AS_SConv, AS_OE, ASM_FLAG,
S);
end
$fclose (h1);
end
endmodule
