Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language (hdl) and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - fpga), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - asic) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of verilog, IEEE 1364-2005.

3298 questions

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My verilog VGA driver causes the screen to flicker (Basys2)

I'm trying to recreate Adventure(1979) in Verilog and so far I have character movement, collision and map generation done. It didn't flicker that much before I separated the maps into modules now it flickers constantly. When I was looking up this…

verilog fpga system-verilog xilinx vga

asked Apr 25 '15 at 04:49

Dilancuan

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Verilog syntax errors

Near "(": syntax error, unexpected '(', expecting ')'. I have no idea why I got errors. //P[0]------------------------------------------ //Y[0], A[0], B[0] and32bit and_inst0(.Y(s0), .A(MCND), .B(32{MPLR[1]})); and32bit…

verilog system-verilog

asked Apr 24 '15 at 04:51

B-Y

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3 answers

How to Embed Systemverilog Interpreter using DPI-C?

Problem Description: I design in SystemVerilog and write the testbenches in the same language. I want to be able to compile my design and test different functions during simulation in the way you would using an interpreter with e. Ideally, I would…

c system-verilog verification system-verilog-dpi

asked Apr 21 '15 at 19:28

Nyarmith

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2 answers

How to pass parameters to a verilog module when performing synthesis?

I have a parameterized verilog module with a bitwidth that is variable depending on the value given in `define WIDTH. However, I would like to be able to somehow change the value of WIDTH by passing in a parameter during synthesis using design…

verilog system-verilog hdl synthesis register-transfer-level

asked Mar 28 '15 at 23:53

Veridian

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QuartusII Synthesis: Enumerated type to State signals (encoding)

I am designing an FSM in SystemVerilog for synthesis through the QuartusII (14.1) tool to put on an Altera FPGA. I am using an enum declaration to make the code much more reasonable: typedef enum logic [7:0] { CMD_INIT, …

enums verilog system-verilog fsm quartus

asked Mar 27 '15 at 19:13

Unn

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Red output running testbench on 4-bit ALU

I'm trying to create a 4-bit ALU in Verilog that does multiplication, addition, BCD addition and concatenation. Here's my code so far: module alu4bit(A,B,S,Y); input [3:0] A, B; input [1:0] S; output [7:0] Y; reg [7:0] Y; wire [7:0] A0, A1, A2,…

verilog system-verilog alu

asked Mar 24 '15 at 17:51

Austin

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For logic implementation in System Verilog

I'm just learning HDL and I'm interested in how a for loop is implemented in System Verilog. With the following code... always_ff(posedge clk) begin for(int i = 0; i < 32; i++) s[i] = a[i] + b[i]; end Will I end up with 32 adders in the logic…

for-loop logic fpga system-verilog hdl

asked Mar 24 '15 at 14:41

George Waller

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2 answers

"Unique case violation" warning at time 0

I have a unique case statement inside an FSM that looks something like this: enum logic [1:0] {IDLE = 2'b01, RUN = 2'b10} state, next_state; always_comb begin next_state=state; unique case(state) IDLE: next_state = RUN; …

system-verilog

asked Mar 23 '15 at 13:48

nguthrie

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Verilog for loops - synthetization

I am pretty new to Verilog, but would like to understand it properly. Currently I am making TxRx on FPGA. I noticed that my code is consuming huge amount of logic, although it should not be like that. So I did not wrote my code properly. I know…

verilog system-verilog hdl

asked Mar 19 '15 at 15:08

elem

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1 answer

Convert binary input into residue number system

I have written a code which converts our number which is in binary into residue using a look up table. First, I have made a memory having both read and write enables and stored values. During 'we' , 'a' is my input which is of 8 bit... for every bit…

verilog fpga system-verilog

asked Mar 11 '15 at 06:48

user4611785

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Option & type_option in System Verilog

Coveegroup x; C: Coverpoint a {type_option.weight=0;} Endgroup I want to set coverpoint C weight to 0, for all the instances of covergroup x. So I have used type_option, as option is for instance specific settings. I have created 4 objects of…

verilog system-verilog vlsi

asked Mar 10 '15 at 15:46

Karan Shah

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Verilog Critical Path

I have determined the following is my critical path (SHA1 algorithm) h0 <= h0 + A; h1 <= h1 + B; h2 <= h2 + C; h3 <= h3 + D; h4 <= h4 + E; When I commented this section of the code out, my Fmax would be around 300Mhz, but with it, it is around…

performance verilog system-verilog

asked Mar 08 '15 at 08:39

Sugihara

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Combinational logic "IF" and "assign" statement in systemverilog

I found a very strange behaviour when design my ALU, hope someone can have a look it and tell me what is going on. Here is the code module adder ( output logic signed[31:0] y, output logic Cout, input logic signed[31:0] a, b, input logic Cin,…

system-verilog alu

asked Feb 27 '15 at 13:33

Shuaiyu Jiang

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1 answer

In SystemVerilog, can events be defined in ports

In Verilog, I know we can't pass "events" between modules. Howe about in System Verilog ? I would like the event "trig" hooking the trigger source blocks "eventGen" and is consumed by the block "eventConsume" Some how I get compilation error…

verilog system-verilog

asked Feb 25 '15 at 02:58

Mike

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Why two exactly "wire" statement in systemverilog, one can be compiled and the other on can not?

Here is the first HDL code for my program counter. timeunit 1ns; timeprecision 10ps; module PC( output logic [31:0] pc_addr, output logic [31:0] Next_addr, input logic [31:0] Branch_addr, input logic PCSrc, input logic clock, reset ); wire [31:0]…

system-verilog

asked Feb 24 '15 at 12:33

Shuaiyu Jiang

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