1
module top();
    event e1;
    evnt i_evnt(e1);

endmodule

module evnt(input event e1);
  /* Program body  

  */
endmodule

when this modules complied it give error

A Verilog keyword was found where an identifier was expected.

How to pass event as argument to module?

Akshay Patil
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  • Your code seems to compile ok. – AldoT Jan 23 '15 at 10:00
  • @AldoT i used irun version 10.20-s104 is there any issue related to simulator version. – Akshay Patil Jan 23 '15 at 10:47
  • @AkshayPatil It also works on EDAPlayground on both Riviera and ModelSim. Incisive 10 is a 4-5 year old version which didn't support the complete SV standard. – Tudor Timi Jan 23 '15 at 10:53
  • @Tudor i tried in EDAPlayground its working. – Akshay Patil Jan 23 '15 at 10:55
  • @Akshay Patil this seems to be a tool specific issue. EDAPlayground-VCS-2014 does not allow this. It throws an error reading, "Non-net variable 'e1' cannot be an input or inout port." BTW you can also replace event by wire/reg and change logic accordingly. – sharvil111 Oct 05 '15 at 09:22

0 Answers0