Lets say there is a signal a
. When the signal goes high, it has to stay high at least for three positive clock edges.
We can write the property as
property p;
@(posedge clk) $rose(a) -> a[*3];
endproperty
The property fails for the case below.
clk _ _ _ | = = = | _ _ _ | = = = | _ _ _ | = = = | _ _ _ | = = = |
a _ _ | = = = | _ _ | = = = = = = = = = = = = = = = = = =
This is not in accordance with the specification where a is going low in the middle but will be pulled high by the next posedge and hence the above assertion wont catch this.
Can anyone tell if there is any way to write assertion to catch this bug?
Thank you