I would like to verify that a bus is stable in an assertion. For example, I would expect the following assertion to flag an error if data
changes in the clock after the re
falling edge.
wire clk, rst_n, re;
wire [15:0] data;
a_chk_stable_data:
assert property (@(posedge clk) disable iff(!rst_n)
($fell(re) |=> $stable(data[15:0])))
else begin
$display("ERROR: one or more bits of data not stable");
end
I believe that $rose
only operates on the LSB of a bus (link). Does $stable
only operate on the LSB as well, or does it support signals of any width?