For logic implementation in System Verilog

Question

I'm just learning HDL and I'm interested in how a for loop is implemented in System Verilog.

With the following code...

always_ff(posedge clk)

begin

for(int i = 0; i < 32; i++) s[i] = a[i] + b[i];

end

Will I end up with 32 adders in the logic and they are all executed simultaneously? Or are the additions performed sequentially somehow?

Thanks Boscoe

possible duplicate of [For-loop in Verilog](http://stackoverflow.com/questions/19394294/for-loop-in-verilog) — Ari, Mar 24 '15 at 22:08

score 4 · Accepted Answer · answered Mar 24 '15 at 15:40

Loops which can be statically unrolled (as per your example) can be synthesised.

The example you gave has to execute in a single clock cycle, there would be nothing sequential about the hardware generated:

Your example :

always_ff(posedge clk) begin
  for(int i = 0; i < 32; i++) begin
    s[i] <= a[i] + b[i];
  end
end

Is just (32 parallel adders):

always_ff(posedge clk) begin
  s[0] <= a[0] + b[0];
  s[1] <= a[1] + b[1];
  s[2] <= a[2] + b[2];
  //...
end

1 Answers1