Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language (hdl) and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - fpga), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - asic) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of verilog, IEEE 1364-2005.

3298 questions

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Is there any method to know whether a member is declared random or not in a class in SV

// Current Class class x; rand int a; int b; // b is nonrandom as of now function new(); endfunction function abc; // if a != ref.a, where ref is reference object of class x, declared somewhere else a.rand_mode(0); …

system-verilog uvm

asked Jul 15 '15 at 18:26

Karan Shah

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verilog power operator ** result size

Can the power operator ** be used with arbitrarily large operands? Ex: reg [100:0] c; reg [15:0] a; reg [15:0] b; c = a**b; Does there is some maximum limit on operand size?

verilog system-verilog

asked Jul 06 '15 at 13:38

quartz

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1 answer

SystemVerilog: Creating an array of classes with different parameters

this topic has a similar question like mine. But they don't figured out any solution. I have defined a class with subclasses. The subclass contains a vector, which width should be different in the array. array[0] class with subclasses and vector…

arrays polymorphism subclass system-verilog

asked Jun 24 '15 at 21:08

William

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2 answers

How SVUnit has been used?

I'm looking for reasons to use SVUnit in my projects. As a software engineer I used to write tests before the production code. However, I don't see so much adoption of this initiative. Why? Is it worth it?

system-verilog

asked Jun 24 '15 at 05:20

antuirno

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1 answer

How to use recursive properties in Systemverilog

The module to be verified is as follows... The module has an input in1 and an output out1, on alternating clock cycles, out1 is the buffered and inverted value of in1. I tried coding the checker module using a recursive property. module check (input…

recursion properties system-verilog assertion system-verilog-assertions

asked Jun 24 '15 at 01:17

Revanth Kamaraj

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2 answers

About the latches generated by "case" syntax

I understand when using case syntax in systemverilog, we need to fully describe all combinations or add a default to avoid latches. Here is my example code, no latches are generated: module test( input logic[2:0] op, output logic a,b,c ); …

mips verilog system-verilog

asked Jun 22 '15 at 13:29

Shuaiyu Jiang

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1 answer

system verilog assertion disable condition

I have this assertion in order to check clk freq: assert property clk_freq; int cnt; @(posedge fast_clk, clk_1MHz) disable_iff(!enable_check) ($rose(clk_1MHz), cnt=0) |=> (!$rose(clk_1MHz),cnt++) [*0:$] ##1 $rose(clk_1MHz),…

system-verilog system-verilog-assertions

asked Jun 22 '15 at 07:50

Meir

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1 answer

Parameter passing in Systemverilog

In the following Systemverilog code snippet: xxx_model # (.inst_name({inst_name,".ce_0"})) ce_0 ( ... .. ); I can't understand this part inst_name({inst_name,".ce_0"}). Kindly help me understand.

system-verilog

asked Jun 22 '15 at 03:36

bang

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2 answers

SystemVerilog DPI returning string from C++ to verilog - ASCII charaters at the end?

I am returning a string from C function to SystemVerilog using DPI. const char* print_input_dpi(int w, int h, int p, ......int mtail){ std::stringstream ss; ss<<"w="<

c++ system-verilog system-verilog-dpi

asked Jun 17 '15 at 22:08

user749632

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importing VHDL packages to SV from libraries other than WORK

I have a VHDL module that is compiled to a library, say, LIB_A. The module has ports that are records, the corresponding type is defined in a package that is also compiled into LIB_A. I would like to write some assertions for the module and check…

vhdl system-verilog assertions

asked Jun 15 '15 at 13:27

Andy

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1 answer

Systemverilog: Simulation error when passing structs as module input\outputs

I am trying to pass one structure as an input and get the output in another structure. However I am having some issues during simulation. The following example code compiles fine in questasim, however the simulation gives the following…

struct system-verilog questasim system-verilog-dpi

asked Jun 05 '15 at 20:03

user3716072

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1 answer

System Verilog 2012 dependency analysis

I am in the process of adapting the System Verilog LRM into Antlr4. This is a huge overkill for what I really need, however. Basically I need dependency analysis similar to the -M switch in gcc. This problem has been surprisingly difficult to solve,…

antlr4 system-verilog

asked Jun 04 '15 at 23:29

sean

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1 answer

Adding skew to improve timing

I want to improve the operating frequency of my design, In the register to register timing analysis I have observed a lot of delay in the combinational elements. This is impacting the timing of the circuit and the slack observed is about -0.3ns , I…

verilog fpga system-verilog register-transfer-level asic

asked May 24 '15 at 09:00

Vamsi

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1 answer

Systemverilog doesn't allow variable declarations after call to super.foo()?

I'm running into a weird issue working with SystemVerilog on DVT. The code snippet in question looks something like this: class parent; int A; function void foo(); A = 5; endfunction endclass class childA extends parent; …

system-verilog

asked May 20 '15 at 16:48

Jan Bartels

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2 answers

Syntax for looping through lower dimension of multidimensional associative array in a constraint

class ns_data_struct; rand bit [63:0] ns_size = 64'h0000_0000_0000_0800; endclass : ns_data_struct class conf; ns_data_struct ns_data[]; function new(); ns_data = new[5]; foreach (ns_data[i]) ns_data[i] = new(); …

system-verilog questasim

asked May 12 '15 at 14:57

Karan Shah

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